Senior DFT Engineer

Veedee Solutions LLP; Chennai; Vor Ort; INR 2.500.000 - 4.500.000; Vollzeit

Zusammenfassung

Veedee Solutions LLP is seeking a Senior DFT Engineer to drive DFT architectures for complex SOC designs in a fast-paced setting.

You will lead scan insertion, fault coverage analysis, and pattern validation while using Tessent for MBIST/ATPG. You’ll collaborate with design teams to integrate DFT features, ensure standards, and mentor junior engineers in DFT practices.

Qualifikationen

• Experience with DFT techniques including scan insertion, MBIST and ATPG.
• Proficiency with Tessent and related DFT tools.
• Experience in fault coverage analysis and test pattern validation.
• Familiarity with SOC design and signoff processes.
• Excellent problem-solving skills and attention to detail.
• Strong communication and teamwork abilities.

Aufgaben

• Develop and implement DFT architectures and methodologies for complex SOC designs.
• Perform scan insertion, test pattern validation, and fault coverage analysis.
• Utilize Tessent for MBIST and ATPG to boost test coverage and efficiency.
• Collaborate with design teams to integrate DFT features into the flow and meet standards.
• Conduct DFT DRC checks and resolve issues during the design process.
• Provide technical guidance and mentorship to junior engineers in DFT practices.

Kenntnisse

DFT techniques

Scan insertion

MBIST

ATPG

Tessent

Fault coverage

Test pattern validation

SOC design

Signoff processes

Problem solving

Teamwork

Communication

Tools

Tessent

Jobbeschreibung

We are seeking a highly skilled Senior DFT Engineer to join our dynamic team. The ideal candidate will have extensive experience in design for testability (DFT) methodologies and will be responsible for ensuring the highest levels of fault coverage and testability in our semiconductor products. As a Senior DFT Engineer, you will work closely with design and verification teams to implement DFT strategies that meet project requirements and timelines.

Key Responsibilities:

• Develop and implement DFT architectures and methodologies for complex SOC designs.
• Perform scan insertion, test pattern validation, and fault coverage analysis to ensure robust testability.
• Utilize tools such as Tessent for MBIST and ATPG to enhance test coverage and efficiency.
• Collaborate with cross-functional teams to integrate DFT features into the design flow and ensure compliance with industry standards.
• Conduct DFT DRC checks and resolve any issues that arise during the design process.
• Provide technical guidance and mentorship to junior engineers in DFT practices and methodologies.

Required Skills:

• Strong knowledge of DFT techniques including scan insertion, MBIST, and ATPG.
• Proficiency in using DFT tools such as Tessent.
• Experience with fault coverage analysis and test pattern validation.
• Familiarity with SOC design and signoff processes.
• Excellent problem-solving skills and attention to detail.
• Strong communication and teamwork abilities.

If you are passionate about DFT and looking to make a significant impact in a fast-paced environment, we encourage you to apply for this exciting opportunity.