Senior DFT Engineer

Veedee Solutions LLP; Navi Mumbai; On-site; INR 2,400,000 - 4,200,000; Full time

Job summary

Veedee Solutions LLP in Navi Mumbai, India seeks a Senior DFT Engineer to join our fast-paced semiconductor team. You will design and implement DFT strategies to maximize fault coverage and testability across complex SOC designs.

You will work with design and verification teams, perform scan insertion, MBIST/ATPG, and use Tessent tools. Mentoring juniors and ensuring DFT DRC checks meet industry standards.

Qualifications

• Experience with DFT for SOC designs.
• Knowledge of scan insertion, MBIST and ATPG.
• Experience with DFT tools like Tessent.
• Experience with fault coverage analysis and test pattern validation.

Responsibilities

• Develop and implement DFT architectures for complex SOC designs.
• Perform scan insertion, test pattern validation, and fault coverage analysis.
• Use Tessent (MBIST/ATPG) to improve test coverage.
• Collaborate with design and verification teams to integrate DFT features into the design flow.
• Conduct DFT DRC checks and resolve issues during the design process.
• Provide mentorship to junior engineers in DFT practices.

Skills

DFT techniques

Scan insertion

MBIST

ATPG

Tessent

Fault coverage

SOC design

Problem solving

Teamwork

Communication

Tools

Tessent

Job description

We are seeking a highly skilled Senior DFT Engineer to join our dynamic team. The ideal candidate will have extensive experience in design for testability (DFT) methodologies and will be responsible for ensuring the highest levels of fault coverage and testability in our semiconductor products. As a Senior DFT Engineer, you will work closely with design and verification teams to implement DFT strategies that meet project requirements and timelines.

Key Responsibilities:

• Develop and implement DFT architectures and methodologies for complex SOC designs.
• Perform scan insertion, test pattern validation, and fault coverage analysis to ensure robust testability.
• Utilize tools such as Tessent for MBIST and ATPG to enhance test coverage and efficiency.
• Collaborate with cross-functional teams to integrate DFT features into the design flow and ensure compliance with industry standards.
• Conduct DFT DRC checks and resolve any issues that arise during the design process.
• Provide technical guidance and mentorship to junior engineers in DFT practices and methodologies.

Required Skills:

• Strong knowledge of DFT techniques including scan insertion, MBIST, and ATPG.
• Proficiency in using DFT tools such as Tessent.
• Experience with fault coverage analysis and test pattern validation.
• Familiarity with SOC design and signoff processes.
• Excellent problem-solving skills and attention to detail.
• Strong communication and teamwork abilities.

If you are passionate about DFT and looking to make a significant impact in a fast-paced environment, we encourage you to apply for this exciting opportunity.