Senior DFT Engineer

Veedee Solutions LLP; Kurnool; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

Veedee Solutions LLP seeks a highly skilled Senior DFT Engineer to join a dynamic team focused on design for testability in semiconductor products. You will implement DFT strategies with senior-level expertise, collaborating with design and verification teams to meet project timelines and quality goals.

Responsibilities include installing DFT architectures, performing scan insertion, MBIST/ATPG, and fault coverage analyses, and mentoring junior engineers.

Qualifications

• Experience with design for testability (DFT) methodologies.
• Strong knowledge of scan insertion, MBIST and ATPG.
• Proficiency with Tessent tools for MBIST/ATPG.
• Experience analyzing fault coverage and validating test patterns.
• Familiarity with SOC design and signoff processes.

Responsibilities

• Develop and implement DFT architectures and methodologies for complex SOC designs.
• Perform scan insertion, test pattern validation, and fault coverage analysis to ensure robust testability.
• Utilize tools such as Tessent for MBIST and ATPG to enhance test coverage and efficiency.
• Collaborate with cross-functional teams to integrate DFT features into the design flow and ensure compliance with industry standards.
• Conduct DFT DRC checks and resolve any issues that arise during the design process.
• Provide technical guidance and mentorship to junior engineers in DFT practices and methodologies.

Skills

DFT techniques

Scan insertion

MBIST

ATPG

Tessent

Fault coverage

SOC design

DFT tooling

Tools

Tessent

Job description

We are seeking a highly skilled Senior DFT Engineer to join our dynamic team. The ideal candidate will have extensive experience in design for testability (DFT) methodologies and will be responsible for ensuring the highest levels of fault coverage and testability in our semiconductor products. As a Senior DFT Engineer, you will work closely with design and verification teams to implement DFT strategies that meet project requirements and timelines.

Key Responsibilities:

• Develop and implement DFT architectures and methodologies for complex SOC designs.
• Perform scan insertion, test pattern validation, and fault coverage analysis to ensure robust testability.
• Utilize tools such as Tessent for MBIST and ATPG to enhance test coverage and efficiency.
• Collaborate with cross-functional teams to integrate DFT features into the design flow and ensure compliance with industry standards.
• Conduct DFT DRC checks and resolve any issues that arise during the design process.
• Provide technical guidance and mentorship to junior engineers in DFT practices and methodologies.

Required Skills:

• Strong knowledge of DFT techniques including scan insertion, MBIST, and ATPG.
• Proficiency in using DFT tools such as Tessent.
• Experience with fault coverage analysis and test pattern validation.
• Familiarity with SOC design and signoff processes.
• Excellent problem-solving skills and attention to detail.
• Strong communication and teamwork abilities.

If you are passionate about DFT and looking to make a significant impact in a fast-paced environment, we encourage you to apply for this exciting opportunity.