Senior Design Verification Engineer

Quest Global; Hyderabad; On-site; INR 2,000,000 - 4,000,000; Full time

Job summary

Quest Global is seeking a Senior Design Verification Engineer to join a dynamic team responsible for SOC and IP verification. The role emphasizes Verilog, SystemVerilog, and UVM expertise to build robust verification environments and testbenches.

You will collaborate with design engineers on protocol specifications (AXI, APB, CHI, USB) and develop verification strategies, including C/C++ support code. Mentorship and process improvement are encouraged.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience in SOC and IP verification with Verilog/SystemVerilog and UVM.
• Proficient in C/C++ and familiar with AXI, APB, CHI, USB protocols.
• Strong analytical and problem-solving skills with good teamwork.

Responsibilities

• Develop and execute verification plans for SOC and IP designs.
• Create and maintain testbenches using Verilog/SystemVerilog.
• Apply UVM-based verification methodologies to improve efficiency.
• Collaborate with design engineers on protocol requirements (AXI, APB, CHI, USB).
• Write verification code in C/C++ to support tasks.
• Analyze and debug design issues and provide feedback.
• Mentor junior engineers and improve verification processes.

Skills

Verilog

SystemVerilog

UVM

C/C++

SOC verification

Digital design

Education

Electrical/Computer Engineering degree

Job description

Job Title: Senior Design Verification Engineer

Job Type: Full-Time

Job Description

We are seeking a highly skilled and experienced Senior Design Verification Engineer to join our dynamic team. The ideal candidate will possess a strong background in SOC and IP verification, with expertise in Verilog, System Verilog, and UVM. You will play a critical role in ensuring the quality and reliability of our designs through rigorous verification processes.

Key Responsibilities

• Develop and execute comprehensive verification plans for SOC and IP designs.
• Utilize Verilog and System Verilog to create and maintain testbenches and verification environments.
• Implement UVM-based verification methodologies to enhance the efficiency and effectiveness of the verification process.
• Collaborate with design engineers to understand specifications and requirements for various protocols, including AXI, APB, CHI, and USB.
• Write and maintain verification code in C/C++ to support advanced verification tasks.
• Analyze and debug complex design issues, providing timely feedback to the design team.
• Mentor junior engineers and contribute to the continuous improvement of verification processes and methodologies.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Proven experience in SOC and IP verification, with a strong understanding of digital design principles.
• Proficiency in Verilog, System Verilog, and UVM.
• Solid programming skills in C/C++.
• Familiarity with industry-standard protocols such as AXI, APB, CHI, and USB.
• Strong analytical and problem-solving skills, with a keen attention to detail.
• Excellent communication and teamwork abilities.

Join us in shaping the future of technology by ensuring the highest standards of design verification. If you are passionate about innovation and excellence, we would love to hear from you!