Verification Engineer

LeadSOC Technologies Pvt Ltd; Bengaluru; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru seeks a Senior Verification Engineer with 5+ years of experience in CPU verification or high-speed protocols (DDR, PCIe, Ethernet, USB). You will design verification plans, build reusable SystemVerilog/UVM environments, and drive coverage closure.

You will develop constrained-random tests, assertions, and scoreboards while mentoring juniors and supporting cross‑functional teams in a fast-paced AI/SoC program.

Qualifications

• 5+ years of hands-on experience in digital design verification.
• Proficient in SystemVerilog and UVM testbench development.
• Experience with functional coverage, assertions, constrained-random verification, and coverage closure.
• Hands-on experience with simulation and debug tools such as VCS, Questa, Xcelium, or Verdi.
• Expertise in CPU Verification, DDR Verification, PCIe Verification, Ethernet Verification, or USB Verification.

Responsibilities

• Develop and execute verification plans for complex IPs, subsystems, and SoCs based on design specs and microarchitecture.
• Build, enhance, and maintain reusable SystemVerilog/UVM verification environments.
• Develop constrained-random and directed tests, sequences, drivers, monitors, and scoreboards.
• Perform functional verification of CPU designs or interfaces involving DDR, PCIe, Ethernet, or USB.
• Define functional coverage models, analyze code and coverage, drive closure.
• Develop assertions and protocol checkers to validate design behavior and identify issues.
• Debug simulation failures, identify root causes, and collaborate with design teams to resolve defects.
• Manage regressions, track verification progress, and communicate risks and closure status.
• Support integration, low-power verification, and gate-level simulation where applicable.
• Mentor junior engineers and participate in technical reviews.

Skills

SystemVerilog

UVM

Functional coverage

Constrained‑random verification

Testbench development

Debugging

Education

Bachelor’s or Master’s degree in Electronics or related engineering

Tools

VCS

Questa

Xcelium

Verdi

Job description

We’re Hiring | Senior Verification Engineers | LeadSoc

We are looking for experienced Verification Engineers with expertise in CPU verification or high-speed protocols such as DDR, PCIe, Ethernet, and USB to join our engineering teams.

Experience: 5+ years

Notice Period: Immediate to 30 days maximum

Key Responsibilities

• Develop and execute verification plans for complex IPs, subsystems, and SoCs based on design specifications and microarchitecture.
• Build, enhance, and maintain reusable SystemVerilog/UVM verification environments.
• Develop constrained-random and directed tests, sequences, drivers, monitors, and scoreboards.
• Perform functional verification of CPU designs or interfaces involving DDR, PCIe, Ethernet, or USB, depending on project requirements.
• Define functional coverage models, analyze code and functional coverage, and drive coverage closure.
• Develop assertions and protocol checkers to validate design behavior and identify corner-case issues.
• Debug simulation failures, identify root causes, and collaborate with design teams to resolve defects.
• Manage regressions, track verification progress, and communicate risks and closure status.
• Support integration, low-power verification, and gate-level simulation where applicable.
• Participate in technical reviews and mentor junior engineers.

Required Skills & Qualifications

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related discipline.
• 5+ years of hands‑on experience in digital design verification.
• Strong proficiency in SystemVerilog and UVM, including testbench development and debugging.
• Experience with functional coverage, assertions, constrained-random verification, and coverage closure.
• Hands‑on experience with simulation and debug tools such as VCS, Questa, Xcelium, or Verdi.
• Strong understanding of digital design fundamentals and IP/subsystem/SoC verification methodologies.
• Expertise in one or more of the following domains:
• Expertise in CPU Verification: Processor architecture, instruction execution, pipelines, interrupts, caches, coherency, and memory subsystems.
• Expertise in DDR Verification: DDR/LPDDR concepts, initialization, memory transactions, timing requirements, and controller/interface verification.
• Expertise in PCIe Verification: Transaction, data link, and physical‑layer concepts; link training, configuration, error handling, and protocol compliance.
• Expertise in Ethernet Verification: MAC/PCS concepts, packet generation and checking, frame handling, flow control, and error scenarios.
• Expertise in USB Verification: USB protocol fundamentals, transfers, enumeration, endpoints, link behavior, and error handling.

Preferred Skills

• Experience integrating and debugging verification IP (VIP).
• Knowledge of AMBA protocols such as AXI, AHB, APB, or CHI.
• Familiarity with scripting languages such as Python, Perl, or Shell.
• Exposure to formal verification, emulation, or low-power verification.
• Strong analytical, communication, and stakeholder collaboration skills.