Job Title: Senior Design Verification Engineer
ACL Digital is seeking experienced Senior Design Verification Engineers with 4+ years of experience. Location options include Bangalore and Hyderabad. Immediate to 30 days notice period preferred.
Key Responsibilities:
- Verify complex test-bench/models using Verilog, System Verilog, or SystemC.
- Debug and troubleshoot verification issues effectively.
- Work on Functional Verification, SoC Verification, and Emulation projects.
- Develop and maintain verification environments using System Verilog, PLI/DPI, C/C++, PERL/Shell scripting, and assembly language.
- Apply OVM/UVM methodology for verification processes.
- Collaborate effectively within a team and communicate clearly.
- Preferably have experience with x86 or ARM SOC architectures and SOC/IP performance verification.
Qualifications:
- Good knowledge of verification flows and debugging skills.
- Experience in complex test-bench/model development.
- Strong programming skills in System Verilog, C/C++, PERL/Shell, and assembly language.
- Knowledge of OVM/UVM methodologies.
- Excellent communication skills and team work ability.
- Experience in architecture domains like x86 or ARM is a plus.
- Background in SOC/IP performance verification is advantageous.
Application:
Interested candidates can share their CVs to sharmila.b@acldigital.com.
About ACL Digital:
ACL Digital, part of the ALTEN Group, specializes in digital engineering and transformation. We empower organizations to thrive in an AI-first world by integrating AI and data-driven solutions from Chip to Cloud.