Senior Design Verification Engineer - Hyderabad

N Human Resources & Management Systems; Hyderabad; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

N Human Resources & Management Systems is seeking a Senior Design Verification Engineer in Hyderabad to own functional verification for blocks and subsystems. You will build and maintain verification environments, drive coverage closure, and ensure silicon-quality signoff before tapeout.

You will lead a team of 3–4 engineers, develop UVM-based testbenches, and collaborate with design and architecture teams to define verification strategies applicable to the project.

Qualifications

• 5+ years of hands-on verification using UVM/SystemVerilog.
• Strong coverage-driven verification methodology.
• Experience with simulation, debug, and regression tools (VCS/Questa).
• Ability to lead 3-4 verification engineers.

Responsibilities

• Develop and maintain UVM-based verification environments and testbenches.
• Write test plans, directed and constrained-random tests, and functional/code coverage models.
• Debug RTL and testbench issues, and drive bugs to closure with design teams.
• Perform assertion-based verification (SVA) and formal verification where applicable.
• Lead and mentor a team of 3-4 verification engineers.
• Own verification signoff and regression health for assigned blocks.
• Collaborate with design, DFT, and architecture teams on verification strategy.

Skills

UVM

SystemVerilog

Coverage-driven verification

Team leadership

Tools

VCS

Questa

Job description

N Human Resources & Management Systems | Full time

We are hiring a Senior Design Verification Engineer to own functional verification for design blocks and subsystems. You will build and maintain verification environments, drive coverage closure, and ensure silicon-quality signoff before tapeout.

Key Responsibilities:

• Develop and maintain UVM-based verification environments and testbenches
• Write test plans, directed and constrained-random tests, and functional/code coverage models
• Debug RTL and testbench issues, and drive bugs to closure with design teams
• Perform assertion-based verification (SVA) and formal verification where applicable
• Lead and mentor a team of 3-4 verification engineers
• Own verification signoff and regression health for assigned blocks
• Collaborate with design, DFT, and architecture teams on verification strategy

Requirements:

• 5+ years of hands-on experience in functional verification using UVM/SystemVerilog
• Strong understanding of coverage-driven verification methodology
• Experience with simulation, debug, and regression tools (VCS/Questa or equivalent)