Senior Design Verification Engineer

L&T Technology Services; Bengaluru; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

A leading technology firm in Bengaluru is seeking a Mid-Senior level engineer specialized in IP/SoC verification. The role involves defining verification plans, developing functional tests, and collaborating with design teams. Candidates should have a Bachelor's or Master's degree in Computer Science or Electronics Engineering and substantial experience in Verilog/UVM methodology. The position is full-time and offers opportunities for growth in a dynamic tech environment.

Qualifications

• 6/10+ years of experience in StemVerilog/UVM methodology.
• Experience in architecting and implementing Design Verification infrastructure.
• Hands-on experience with ARM/RISC-V based CPU sub-systems.

Responsibilities

• Define and implement IP/SoC verification plans.
• Develop functional tests based on verification test plans.
• Drive Design Verification to closure based on defined metrics.

Skills

Verilog/UVM methodology

C/C++ based verification

Python

TCL

Perl

Shell scripting

Education

Bachelor's or Master's degree in Computer Science or Electronics Engineering

Tools

Version control systems (Mercurial, Git, SVN)

Job description

Overview

DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification. Develop functional tests based on verification test plan. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. Debug, root-cause and resolve functional failures in the design, partnering with the Design team.

Responsibilities

• Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification
• Develop functional tests based on verification test plan
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
• Debug, root-cause and resolve functional failures in the design, partnering with the Design team

Qualifications

• Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience
• 6/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification
• 6/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies
• Experience in development of UVM based verification environments from scratch
• Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
• Experience with verification of ARM/RISC-V based CPU sub-stems or SoCs
• Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet
• Experience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
• Experience with revision control stems like Mercurial(Hg), Git or SVN

Seniority level

• Mid-Senior level

Employment type

• Full-time

Job function

• Information Technology, Administrative, and Business Development

Industries

• Software Development and IT Services and IT Consulting