Senior Design Verification Engineer

Anlage Digital; Bengaluru; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

Anlage Digital in Bengaluru, India, seeks an experienced verification engineer to lead pre-silicon verification for high-quality silicon. The candidate will develop SV/UVM environments, define verification plans, and drive coverage closure while producing regular progress reports.

The role requires 9–18 years in semiconductor verification, experience with regression tooling, and collaboration across international teams. English communication must be strong.

Qualifications

• Bachelor or Master degree in EE/CE as listed.
• 9–18 years of experience in semiconductor pre-silicon verification.
• Role focuses on high quality silicon free of functional bugs via pre-silicon verification.

Responsibilities

• Develop System Verilog compliant verification environments.
• Create verification plans and drive coverage closure.
• Provide progress reports and manage regressions.

Skills

SystemVerilog/UVM

Specman E

MATLAB modelling

Regression analysis

Coverage analysis

Test bench qualification

Functional safety

Jenkins automation

C modelling

English communication

Cross-functional teamwork

International teams

Perl scripting

Python scripting

Education

Bachelor/Master in EE/CE

Tools

Xcelium

Vmanager

SystemVerilog

VHDL

SpecMan e

Jenkins

Python

Perl

Job description

Qualification B.E / M.E / M.Tech or B.S / M.S in EE / CE

Experience Level 9-18 years

Role Objectives

• High quality silicon with no functional bugs by performing high quality pre-silicon verification

Key Responsibilities

• Develop System Verilog compliant verification environments
• Creation of verification plans and execution of coverage closure
• Provide relevant reports to show progress
• Run regressions / help set up automatic regressions

Skillset

• Proven working experience within the semiconductor industry in constraint
• random functional and formal verification
• Expertise in hardware verification using SystemVerilog/UVM. Also,
• preferably expertise in Specman E or willingness to learn on the job.
• Experience with mixed-signal IP with RNM/Verilog A model, Experience in
• C modelling for Digital Signal blocks
• Experience in MATLAB modelling is an added advantage
• Knowledge of using regression and coverage analysis tools, as well as
• knowledge of test bench qualification
• Knowledge and experience with functional safety according to ISO26262
• Working experience in international and cross-functional technical teams
• within a multi-cultural environment
• Excellent English communication skillst.
• Qualified verification environment using SystemVerilog and SpecMan e
• Intermediate progress / KPI status reports on agreed frequency
• Debug support to reach sign-off quality targets of IPs
• Automation for regression runs (Jenkins) Certitude closure

Tools

• Xcelium, Vmanager Enterprise edition, System Verilog, VHDL, knowledge of
• scripting languages – perl / python, automation scripts with Jenkins