Senior Design Engineer

Eximietas Design; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Eximietas Design in Bengaluru is looking for ASIC/SoC design engineers with 7–20 years of experience to join long-term ODC projects. You will write specifications, craft micro-architecture diagrams, and implement RTL using SystemVerilog.

Expect responsibilities in synthesis, timing closure, and collaboration with verification teams to ensure high-performance multi-core processor designs. Ideal candidates bring deep microarchitecture knowledge and extensive experience with RTL coding, front-end

Qualifications

• Write design specifications for chip blocks and create micro-architecture diagrams.
• Design functional blocks using SystemVerilog RTL code.
• Conduct synthesis and routing to meet timing/area goals.
• Collaborate with verification engineers to ensure correctness.

Responsibilities

• Write design specifications for different functional blocks on a chip, create micro-architecture diagrams of functional blocks, design functional blocks using System Verilog RTL code, and conduct synthesis and route to meet timing / area goals
• Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Static Timing Analysis (STA)
• Contribute to Design Verification, Synthesis, Power Reduction, Timing Convergence & Floorplan efforts
• Responsible for logic implementation of complex design block(s) using RTL coding techniques (Verilog)
• Code Verilog RTL for high performance designs with supervision from manager and input from peers and architects in the engineering team
• You handle Verilog RTL logic design and debug
• Develop RTL for logic blocks and participate in Front End activities like Synthesis, Timing Closure & FPGA implementation
• Contribute as a design engineer developing the next-generation of multi-core processors
• Specify, design, and synthesize RTL blocks, optimize and floorplan them
• Work with verification engineers to ensure accuracy.

Skills

Microarchitecture

SystemVerilog RTL coding

RTL debugging

Synthesis

Timing closure

Front End collaboration

Tools

SystemVerilog

Synthesis

STA

Linting

CDC Analysis

Floorplanning

Equivalence Checking

Verilog

Job description

• ASIC/SoC Design position is your opportunity to join one of the industry’s leading companies in Smart Edge SoCs for network/systems control, management security systems, and IIoT. You should have prior knowledge of logic design and computer architecture.

Skills:

Microarchitecture, PCIe, USB, Ethernet, DDR3/4, LPDDR, AXI, I2C/I3C, SPI, SD/SDIO/eMMC, UART, PTPX, Optimisation, 2/3/4/5/6nm nodes.

We are looking for candidates with 7–20 years of experience who can join with us and part of ODC long term project.

• Write design specifications for different functional blocks on a chip, create micro-architecture diagrams of functional blocks, design functional blocks using System Verilog RTL code, and conduct synthesis and route to meet timing / area goals
• Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Static Timing Analysis (STA)
• Contribute to Design Verification, Synthesis, Power Reduction, Timing Convergence & Floorplan efforts
• Responsible for logic implementation of complex design block(s) using RTL coding techniques (Verilog)
• Code Verilog RTL for high performance designs with supervision from manager and input from peers and architects in the engineering team
• You handle Verilog RTL logic design and debug
• Develop RTL for logic blocks and participate in Front End activities like Synthesis, Timing Closure & FPGA implementation
• Contribute as a design engineer developing the next-generation of multi-core processors
• Specify, design, and synthesize RTL blocks, optimize and floorplan them
• Work with verification engineers to ensure accuracy.

Thanks,