Senior Analog & Mixed-Signal (AMS) Circuit Designer

Qailash Labs; NTR; Hybrid; INR 2,500,000 - 4,200,000; Full time

Job summary

Qailash Labs in Vijayawada is seeking a Senior AMS Designer to lead custom schematic design, transistor sizing, and SPICE model verification for high-precision sensor front-ends. You will drive microarchitecture, PPA optimization, and post-layout parasitic verification in a hybrid work setup.

Required: 4+ years in Analog/Mixed-Signal IC design, Cadence Virtuoso, SPICE models (BSIM-IMG/BSIM4/PSP), and SystemVerilog-AMS. Familiarity with SDL and Cadence Calibre PEX is beneficial.

Qualifications

• M.Tech or Ph.D. in Microelectronics / VLSI Design / Electrical Engineering.
• 4+ years of hands-on experience in custom Analog/Mixed-Signal IC design.
• Direct experience with SPICE model cards (BSIM-IMG, BSIM4, PSP) and Spectre corner setups.
• Expertise in Cadence Virtuoso, Spectre SPICE, SystemVerilog-AMS, and PEX parasitic extraction workflows.
• Strong understanding of low-power analog architectures and PPA optimization.

Responsibilities

• Own microarchitecture and custom schematic implementation of front-end blocks and CDS noise-reduction structures.
• Perform multi-corner SPICE simulations across PVT corners.
• Architect, size, and simulate high-resolution SAR ADCs within tight power envelopes.
• Design precision bandgap references and LDOs; optimize bias current networks.
• Conduct Monte Carlo, noise spectral density, and multi-corner SPICE regressions in Cadence environments.
• Collaborate with layout engineers for SDL and post-layout parasitic extraction.
• Develop Verilog-A / SystemVerilog-AMS behavioral models for full-chip co-simulation.

Skills

Analog IC design

SPICE modeling

Cadence Virtuoso

SystemVerilog-AMS

PPA optimization

Parasitic extraction

Schematic-driven layout

Education

M.Tech or Ph.D. in Microelectronics / VLSI Design / Electrical Engineering

Tools

Cadence Spectre SPICE

Siemens Calibre PEX

Job description

Role Level: Senior AMS Designer Full-Time

Location: Vijayawada / Hybrid (Flexible)

Experience: 4+ years in Custom AMS Circuit Design & SPICE Modeling (or graduating M.Tech/Ph.D. Scholar)

Role Overview:

Lead custom schematic design, transistor sizing, compact SPICE model verification, and AMS simulation of low-noise sensor front-ends, high-resolution data converters, and precision bias circuits. Drive microarchitecture definition, PPA optimization, and post-layout parasitic verification.

Key Responsibilities:

• Own microarchitecture and custom schematic implementation of low-noise front-end charge amplifiers (CTIA), sample-and-hold stages, and Correlated Double Sampling (CDS) noise-reduction arrays.
• Perform multi-corner SPICE simulations across PVT corners (SS, FF, TT)
• Architect, size, and simulate high-resolution, low-power column-parallel SAR ADCs operating within tight power envelopes.
• Design precision bandgap voltage references, Low Dropout (LDO) regulators, and low-noise bias current distribution networks.
• Perform extensive Monte Carlo mismatch simulations, noise spectral density analyses, and multi-corner SPICE regressions in Cadence Spectre.
• Collaborate with layout engineers to perform schematic-driven layout (SDL), critical net shielding, and post-layout parasitic extraction (Siemens Calibre PEX / Cadence Quantus).
• Develop Verilog-A / SystemVerilog-AMS behavioral models for full-chip co-simulation and automated regression testing.

Qualifications & Technical Skills:

• M.Tech or Ph.D. in Microelectronics / VLSI Design / Electrical Engineering.
• 4+ years of hands‑on experience in custom Analog/Mixed‑Signal IC design.
• Direct experience working with SPICE model cards, compact device parameters (BSIM-IMG, BSIM4, PSP), and Spectre corner setups.
• Expertise in Cadence Virtuoso, Spectre SPICE, SystemVerilog-AMS, and PEX parasitic extraction workflows.
• Strong understanding of low‑power analog architectures, noise minimization, and PPA optimization.