Senior Analog Design Engineer

PI Semiconductor; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

PI Semiconductor seeks an experienced analog/mixed-signal IC design engineer in Bengaluru to own end-to-end design cycles. You will develop blocks like bandgap references, LDOs, oscillators, and high‑voltage interfaces while driving simulations, layout guidance, and post‑layout verification.

Collaboration with cross‑functional teams ensures product-level success. The role requires expertise with CMOS analog design, device physics, noise and stability, and hands-on experience with Cadence

Qualifications

• BSEE/MSEE/PhD in Electrical Engineering or related field.
• 5+ years of hands-on analog or mixed-signal IC design experience.
• Strong fundamentals in CMOS analog design, device physics, feedback systems, noise, mismatch, stability, sampling circuits, and layout-dependent effects.
• Experience with precision references, regulators, amplifiers, ADC/DAC circuits, sensor interfaces, oscillators, high-voltage analog circuits, or power management blocks.
• Proficiency with Cadence Virtuoso, Spectre, ADE, Monte Carlo analysis and post-layout extraction flows.
• Ability to debug complex analog issues using simulation and silicon data.

Responsibilities

• Design and develop analog and mixed-signal IC blocks such as bandgap references, LDOs, bias circuits, oscillators, amplifiers, comparators, ADC/DAC support circuits, current/voltage sensing circuits, level shifters, and high-voltage interface circuits
• Own the full design cycle from specification definition, architecture selection, transistor-level design, simulation, layout guidance, post-layout verification, silicon bring-up, characterization, and production support.
• Perform detailed simulations across PVT, mismatch, Monte Carlo, noise, stability, transient, startup, PSRR, CMRR, and reliability conditions.
• Work closely with layout engineers to guide floorplanning, matching, shielding, routing, parasitic-aware layout, ESD/latch-up considerations, and post-layout debug.
• Collaborate with digital, verification, applications, test, product, and systems teams to ensure the design meets product-level requirements.
• Analyze silicon measurement results, correlate silicon behavior with simulation, identify root causes, and drive design fixes when needed.
• Support design documentation, design reviews, FMEA, production test definition, and customer/debug activities as required.

Skills

Analog design

Mixed-signal design

Circuit simulation

Cadence tools

Layout techniques

Verilog-A modeling

Problem solving

Education

BSEE/MSEE/PhD

Tools

Cadence Virtuoso

Spectre

ADE

Monte Carlo

Corner simulations

Post-layout extraction

Job description

Role Responsibilities

• Design and develop analog and mixed-signal IC blocks such as bandgap references, LDOs, bias circuits, oscillators, amplifiers, comparators, ADC/DAC support circuits, current/voltage sensing circuits, level shifters, and high-voltage interface circuits
• Own the full design cycle from specification definition, architecture selection, transistor-level design, simulation, layout guidance, post-layout verification, silicon bring-up, characterization, and production support.
• Perform detailed simulations across PVT, mismatch, Monte Carlo, noise, stability, transient, startup, PSRR, CMRR, and reliability conditions.
• Work closely with layout engineers to guide floorplanning, matching, shielding, routing, parasitic-aware layout, ESD/latch-up considerations, and post-layout debug.
• Collaborate with digital, verification, applications, test, product, and systems teams to ensure the design meets product-level requirements.
• Analyze silicon measurement results, correlate silicon behavior with simulation, identify root causes, and drive design fixes when needed.
• Support design documentation, design reviews, FMEA, production test definition, and customer/debug activities as required.

Required Qualifications

• BSEE/MSEE/PhD in Electrical Engineering or related field.
• 5+ years of hands-on analog or mixed-signal IC design experience.
• Strong fundamentals in CMOS analog design, device physics, feedback systems, noise, mismatch, stability, sampling circuits, and layout-dependent effects.
• Experience designing one or more of the following: precision references, regulators, amplifiers, ADC/DAC circuits, sensor interfaces, oscillators, high-voltage analog circuits, or power management blocks.
• Strong experience with Cadence Virtuoso, Spectre, ADE, Monte Carlo analysis, corner simulations, and post-layout extraction flows.
• Ability to debug complex analog issues using simulation and silicon data.
• Good understanding of layout techniques for precision analog design, including matching, common-centroid layout, guard rings, isolation, shielding, and parasitic control.
• Ability to work independently, take ownership of blocks, and drive them to tapeout-quality completion.

Preferred Qualifications

• Experience with BCD, high-voltage CMOS, automotive, industrial, battery management, optical control, or precision sensing products.
• Experience with sigma-delta ADCs, SAR ADCs, current sensing, temperature sensors, bandgaps, LDOs, charge pumps, or isolated/high-voltage interfaces.
• Familiarity with reliability checks, ESD/latch-up constraints, EM/IR, antenna, DRC/LVS, and foundry design rules.
• Experience with silicon bring-up, bench characterization, ATE correlation, and production yield improvement.
• Knowledge of Verilog-A modeling, MATLAB/Python data analysis, or mixed-signal verification is a plus.

Desired Attributes

• Strong analytical and debugging mindset.
• Practical, silicon-oriented design judgment.
• Ability to balance performance, area, power, schedule, and risk.
• Good communication skills and ability to work across global engineering teams.
• Comfortable working in a fast-paced startup environment with high ownership and limited hand-holding.