Analog Design Engineer

eInfochips (An Arrow Company); Bengaluru; On-site; INR 1,500,000 - 3,000,000; Full time

Job summary

eInfochips (An Arrow Company) in Bengaluru seeks an experienced analog designer with 5-10 years in high-performance analog/mixed-signal design, including RFIC blocks such as PLLs, LNA, and mixer. You will architect and implement building blocks, optimize across process geometries, and collaborate with foundry and layout teams.

Proficiency with Cadence Virtuoso, Spectre, HSPICE, Calibre, and scripting (Python/SKILL/Tcl) is required to drive automated verification and robust designs.

Qualifications

• 5–10 years of analog/mixed-signal design experience.
• Experience with CT sigma delta ADC, RFIC design elements like LNA and mixer.
• Exposure to Cadence Virtuoso and simulation tools (Spectre, HSPICE).
• Experience with Calibre or IC Validator for physical verification.

Responsibilities

• Architect and design high-performance analog/mixed-signal blocks.
• Translate designs across process nodes (28nm to 16nm/7nm).
• Perform pre-layout and post-layout simulations, including Monte Carlo and corner analysis.
• Drive best practices in analog design methodology and automated verification.

Skills

Analog design

RFIC design

PLL design

LNA design

Schematic capture

Tools

Cadence Virtuoso

Spectre/HSPICE

Mentor Calibre

IC Validator

Job description

• Analog designer with experience of 5 to 10 Years of experience in below,
• CT sigma delta ADC, RFIC design: LNA and mixer, PLLs
• Circuit Architecture & Design: Architect and design high-performance analog/mixed-signal building blocks (e.g., PLLs, ADCs/DACs, RFIC).
• EDA exposure: Custom Design/Schematic: Cadence Virtuoso (ADE/Maestro). Simulation: Spectre, HSPICE, or CustomSim. Physical Verification: Mentor Calibre (DRC/LVS/PEX) or Synopsys IC Validator. Reliability/Sign-off: Experience with Voltus, RedHawk, or similar power/IR integrity tools
• Multi-Node Design: Translate and optimize designs across different process geometries, including transition strategies from Planar (e.g., 28nm) to FinFET (e.g., 16nm, 7nm…) nodes.
• Simulation & Verification: Perform comprehensive pre-layout and post-layout simulations, including Monte Carlo, corner analysis, noise analysis, and reliability modeling (EM/IR/Aging/BTI/HCI).
• Methodology: Drive best practices in analog design methodology, including the adoption of automated design tools and script-based verification (Python/SKILL/Tcl).