Senior Analog Layout

ASICtronix and TechSoft Pvt Ltd; Bengaluru; Hybrid; INR 1,200,000 - 1,800,000; Full time

Benefits offered by this job

Hybrid work model

Job summary

ASICtronix and TechSoft Pvt Ltd in Bengaluru is seeking an experienced Analog/AMS Layout Engineer for an immediate hybrid role. You will design and optimize AMS/PMIC layouts, handle IPs independently, and perform complete verification across cross-functional teams.

The role requires 7–10 years in layout/mask design with strong knowledge of layout techniques, clock routing, ESD and experience with 16nm to 7nm nodes. A degree in ECE/EEE or Diploma is needed.

Qualifications

• Proficiency in Layout/mask design with 7–10 years experience.
• Expert knowledge in Layout Design Techniques including matching, clock routing and ESD compliance; experience in Analog, Mixed-Signal design processes.
• Strong skills in debugging Parasitic Extraction, crosstalk, EMIR mitigation, and physical verification (DRC, LVS, PM & Signoff checks).
• Experience with 16nm to 7nm FF technology nodes in submicron and deep-submicron processes.
• Bachelor’s or Master’s degree in ECE, EEE & Diploma.

Responsibilities

• Design and optimization of AMS, PMIC layouts.
• Handle IPs independently and perform complete verification.
• Collaborate with cross-functional teams and review layout designs for client compliance.

Skills

Layout design

Clock routing

ESD compliance

Parasitic extraction

EMIR mitigation

Physical verification

Analog design

Mixed-signal design

DRC

LVS

Signoff checks

Education

Bachelors in ECE/EEE

Diploma

Job description

We are looking for an #Analog_Layout, #IC_Layout, #AMS_Layout Engineer, #immediately based in Bengaluru, with hybrid model. Responsibilities include the design and optimization of AMS, PMIC layouts, handling IP's independently and complete verification. Collaborating with cross-functional teams, you will review layout designs for compliances as per client requirements.

Qualifications

• Proficiency in Layout/mask design with an experience from 7-10 years.
• Expert knowledge in Layout Design Techniques matching, clock routing and ESD compliance, as well as experience in Analog, Mixed-Signal Design processes.
• Strong skills in debugging Parasitic Extraction, crosstalk, EMIR mitigation, and physical verification (DRC, LVS, PM & Signoff checks).
• Experience with 16nm to 7nm FF technology nodes in submicron and deep-submicron processes.
• Bachelor’s or Master’s degree in ECE, EEE & Diploma.