Semiconductor Design Engineer

Crintell Technologies LLC.; Hyderabad; On-site; INR 900,000 - 1,200,000; Full time

Job summary

Crintell Technologies LLC in Hyderabad is seeking a hands-on semiconductor engineer to join a distributed team working onsite. You will collaborate with US counterparts on IP packaging deliverables and apply your chip design and DV knowledge to package, validate, and release IP for downstream use.

The role emphasizes debugging complex multi-component systems, partnering with design, DV, and build-system owners, and exploring AI-assisted workflows.

Qualifications

• 2-5 years of relevant professional experience in semiconductor design, verification, IP packaging, or related engineering domains.
• Understanding of chip design fundamentals and DV basics (RTL concepts, testbenches, simulation flows).
• Experience debugging complex systems (tracing failures across tools, scripts, or flows to root cause).
• Excellent written and verbal communication across time zones.

Responsibilities

• Work onsite at Hyderabad as part of a distributed engineering team, collaborating with US-based counterparts on IP packaging deliverables.
• Apply foundational knowledge of chip design and design verification (DV) concepts to properly package, validate, and release IP for downstream consumption.
• Debug complex, multi-component systems including packaging pipelines, build flows, and design/verification environments to isolate root causes and drive fixes.
• Partner with design, DV, and build-system owners to understand IP requirements and ensure packaged deliverables meet quality and integration standards.
• Identify opportunities to apply AI tools to streamline packaging, debugging, or documentation workflows.
• Clearly document findings, issues, and packaging decisions, and communicate status and blockers proactively to stakeholders.

Skills

Chip design fundamentals

Design verification basics (RTL, testb

IP packaging

Debugging complex systems

Analytical thinking

Effective communication

Education

Tools

CI/CD pipelines

Job description

Key Responsibilities:Work onsite at Hyderabad as part of a distributed engineering team, collaborating closely with US-based counterparts on IP packaging deliverablesApply foundational knowledge of chip design and design verification (DV) concepts to properly package, validate, and release IP for downstream consumptionDebug complex, multi-component systems including packaging pipelines, build flows, and design/verification environments to isolate root causes and drive fixesPartner with design, DV, and build-system owners to understand IP requirements and ensure packaged deliverables meet quality and integration standardsIdentify opportunities to apply AI tools to streamline packaging, debugging, or documentation workflowsClearly document findings, issues, and packaging decisions, and communicate status and blockers proactively to stakeholdersRequired Qualifications:2-5 years of relevant professional experience in semiconductor design, verification, IP packaging, or related engineering domainsWorking understanding of chip design fundamentals and design verification (DV) basics (e.g., RTL concepts, testbenches, simulation flows)Demonstrated experience debugging complex systems (e.g., tracing failures across tools, scripts, or design/verification/packaging flows to root cause)High analytical skills able to break down ambiguous or multi-layered problems methodicallyExceptional written and verbal communication skills able to clearly explain technical issues and status to both engineering peers and management across time zonesWillingness and ability to work onsite at the Hyderabad office.Preferred Qualifications (Big Plus)Understanding of hardware or software build systems (e.g., build orchestration, dependency management, CI/CD pipelines)