ASIC Design Engineer, DMTS/SMTS/MTS Hyderabad, Telangana, India

Micron Technology, Inc.; Hyderabad; On-site; INR 1,500,000 - 2,300,000; Full time

Job summary

Micron Technology, Inc. in Hyderabad is seeking an ASIC Design Engineer to own CAD tools, automation frameworks, design flows and methodologies for memory, SoC, and related products.

You will drive floorplanning, power planning, placement, timing closure, signoff, DFT strategies, and multi-pattern verification, collaborating with architecture, RTL, verification, and test teams to ensure successful tape-out and robust silicon.

Qualifications

• Bachelor's or Master's in EE/CE/CS or equivalent experience.
• Strong knowledge of VLSI/CMOS fundamentals.
• Experience with industry EDA tools for implementation and signoff.
• Proficiency in scripting languages to automate workflows.

Responsibilities

• Own CAD tools development, deployment, and support for flows.
• Create automate scripts to enhance engineering workflows.
• Evaluate AI-assisted solutions to improve productivity.
• Lead floorplanning, timing closure, and signoff activities.
• Support tape-out and silicon bring-up with cross-functional teams.

Skills

VLSI fundamentals

CMOS fundamentals

Python scripting

Tcl scripting

Shell scripting

C/C++

Java

Automation

Unix/Linux

Education

Bachelor's or Master's in EE/CE/CS

Equivalent practical experience

Tools

Cadence Innovus

Cadence Virtuoso

Synopsys ICC2

Synopsys PrimeTime

Siemens Tessent

Cadence Tempus

Cadence Modus

Job description

## ASIC Design Engineer, DMTS/SMTS/MTSHyderabad, Telangana, IndiaApply NowFind out how well you match with this jobJob ID: JR114285**Our vision is to transform how the world uses information to enrich life for *all*.**Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.**Key Responsibilities****Design and CAD Enablement*** Own the development, deployment, and support of scalable CAD tools, automation frameworks, design flows, and methodologies for NAND, DRAM, HBM, SoC, mixed-signal, and other advanced semiconductor products.* Develop, improve, and maintain infrastructure for circuit build capture, layout, simulation, characterization, implementation, physical verification, and signoff workflows.* Create robust software and scripts using Python, Tcl, SKILL, Shell, Perl, C/C++, Java, Lisp, or related languages to automate engineering workflows, analytics, and quality checks.* Evaluate and integrate advanced EDA technologies, AI-assisted engineering solutions, and emerging methodologies to improve productivity, scalability, and silicon quality.* Validated ability to demonstrate AI‐assisted (vibe) coding techniques to improve efficiency or automate design and analysis methodologies Leverage AI tools to automate the tools and workflow Applying Artificial Intelligence in workflows to improve build efficiency* undefined* undefined* Lead implementation and signoff activities across physical design, static timing analysis, and design for test for complex digital, memory, SoC, or mixed-signal products.* Drive floor planning, power planning, placement, clock tree synthesis, routing, optimization, timing closure, and physical verification to meet power, performance, area, reliability, and schedule targets.* Own multi-mode, multi-corner timing signoff, including constraints, setup and hold analysis, timing exceptions, signal integrity, ECOs, and closure across implementation achievements.* Develop and implement DFT strategies, including scan insertion, ATPG, MBIST, LBIST, compression, verification, and silicon bring-up support to achieve manufacturing test coverage goals* Analyze and resolve congestion, IR drop, electromigration, clocking, signal integrity, and implementation issues throughout the design cycle. **Analog and Custom Layout*** Give to next-generation products through the design, optimization, and physical implementation of memory, logic, and analog circuits* Lead custom layout activities, including floor planning, device placement, routing, matching, parasitic-aware optimization, and layout quality reviews.* Perform parasitic extraction and modeling, and support circuit simulation, design validation, reticle experiments, tape-out revisions, and post-layout correlation.* Complete layout and circuit verification using industry-standard simulation, extraction, DRC, LVS, and reliability verification tools **Technical Leadership and Teamwork** * Partner with architecture, RTL, circuit design, verification, methodology, process technology, modeling, standards, product engineering, probe, assembly, test, and marketing teams to ensure design readiness and manufacturability Drive standardization, documentation, training, user support, best-practice adoption, and continuous methodology improvement across global engineering teams.* Provide technical leadership, mentorship, and subject-matter expertise; influence tool, flow, and methodology roadmaps while solving complex multi-functional challenges.* Support tape-out, first-pass silicon success, production ramp, and interpersonal learning through focused execution and effective collaboration. **Qualifications*** Bachelor's or Master's degree or equivalent experience in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent proven experience. Strong knowledge of VLSI and CMOS fundamentals, semiconductor build methodologies, and tradeoffs involving power consumption, efficiency, size, dependability, and manufacturability.* Hands-on experience with industry-standard EDA environments for implementation, timing, test, simulation, extraction, layout, verification, and signoff. Relevant tools may include Cadence Innovus and Virtuoso, Synopsys ICC2 and PrimeTime, Siemens Tessent, Cadence Tempus and Modus, or equivalent platforms.* Proficiency in Unix/Linux environments and one or more engineering programming or scripting languages such as Python, Tcl, SKILL, Shell, Perl, C/C++, Java, or Lisp. Demonstrated ability to develop maintainable automation, debug complex design and flow issues, analyze engineering data, and drive designs to closure.