Staff Engineer IP Verification - Digital Design Verification Hyderabad, Telangana, India Posted 8 hours ago

Micron Technology, Inc.; Hyderabad; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

Micron Technology, Inc. in Hyderabad, India, seeks a Staff Engineer to own verification of complex DRAM IP and subsystems. You will lead verification efforts, define methodologies, and mentor engineers across distributed teams to drive quality and efficiency in RTL verification.

You will develop SV/UVM based testbenches, run directed and random tests, and analyze coverage to push tapeout readiness, while collaborating on advanced DRAM memory flows and AI-assisted verification tools.

Qualifications

• Understand design specifications and define verification scope, strategy, and plans for block/chip RTL verification.
• Develop, execute, and maintain testbenches and test vectors using SV-UVM and digital simulation tools.
• Run directed and constrained-random tests and regressions; analyze results and triage failures.
• Close functional and code coverage metrics; identify holes toward tapeout readiness.
• Provide verification support by simulating, analyzing, and debugging RTL; develop test cases to increase DRAM coverage.
• Co-work with international colleagues on new verification flows for DRAM and memory design.

Responsibilities

• Understand design specifications and define verification scope, strategy, and plans for block/chip RTL verification.
• Develop testbenches and test vectors; run regressions to improve coverage and reliability.
• Debug RTL/testbench issues and coordinate with design teams to identify fixes.

Skills

SV-UVM

Python

Perl

Digital verification

RTL verification

Mentoring

Technical leadership

AI tools

Education

Bachelor’s degree in Electronics Engineering

Postgraduate degree in Electronics or related field

Tools

Virtuoso

XcelIum

SimVision

Verdi/Verisium

Job description

## Staff Engineer IP Verification - Digital Design VerificationHyderabad, Telangana, IndiaApply NowFind out how well you match with this jobJob ID: JR110929**Our vision is to transform how the world uses information to enrich life for *all*.**Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.Complete ownership of verification and end to end analysis of complex block level custom designs with advanced low power and power management technologies spread across multiple categories such as DDR5, LPDDR5, DDR6 and LPDDR6 that are capable of operating at high speeds of up to 11,4000MT/s.**Staff-Level Expectations:****At the Staff level, engineers are expected to:*** **Lead verification efforts for strategic IPs and complex subsystems.*** **Influence verification methodology across projects.*** **Mentor junior engineers and drive verification quality, productivity, and innovation.*** **Provide technical leadership across geographically distributed teams.*** **Ability to lead team, guide and set the direction for the verification effort for any project that the team undertakes.*** **Define roadmap and future scope of verification methodologies.****Roles and Responsibilities:*** Understand design specifications and define verification scope, strategy, and plans for block/chip RTL verification* Develop, execute, and maintain verification testbenches and test vectors using digital simulation tools and methodologies (SV-UVM)* Run directed and constrained-random tests and regressions; analyze results and triage failures.* Close verification metrics (functional coverage / code coverage as applicable) and identify verification holes to demonstrate readiness toward tapeout* Provide verification support to design projects by simulating, analyzing, and debugging block level RTL. Develop Test cases/Stimulus to increase the functional coverage for all DRAM architectures and features.* Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design.* Debug RTL / testbench / environment issues and partner with design engineers to identify root cause, propose fixes, and prevent recurrence.* Provide verification status and summaries to stakeholders; communicate risk clearly and drive action closure.* Good understanding of digital circuits and experience in RTL Verification. Understand the usage of tools like Virtuoso, Xcellium, Simvision, Verdi/Verisium.* Hands on experience in building SV, UVM based Verification testbenches at Block Level.* Good scripting skills using perl, python* Previous work experience in DRAM memory related fields and Must possess good communication, debugging skills and ability to work well in a team.* **Should be proactive in exploring and leveraging AI-related tools in day-to-day tasks.*** **Proactively adopt approved AI tools to support verification workflows, scripting, and methodology improvements, maintaining full responsibility for technical decisions.****Bachelor’s with 7-9 years of experience or Post Graduate Degree in Electronics Engineering or related engineering field required with 6 - 8 years of experience.**