IP Packaging Engineer - 0442

Sunrise Biztech Systems; Hyderabad; On-site; INR 600,000 - 900,000; Full time

Job summary

Sunrise Biztech Systems Pvt. Ltd. in Hyderabad is hiring an IP Packaging Engineer to work onsite with a distributed engineering team and package IP for downstream use.

The role requires a foundation in chip design and DV concepts, debugging of packaging and DV/packaging flows, and collaboration with design and build-system owners. Familiarity with AI tooling to streamline workflows is a plus. This is a 1-year contract.

Qualifications

• 1–2 years of experience in semiconductor design, verification, or IP packaging.
• Working knowledge of RTL concepts, testbenches and simulation flows.
• Experience debugging complex packaging and DV/integration issues.

Responsibilities

• Work onsite at Hyderabad as part of a distributed engineering team.
• Package, validate, and release IP for downstream consumption.
• Debug packaging pipelines and associated build/verification environments.
• Collaborate with design, DV, and build-system teams to meet IP requirements.
• Identify opportunities to apply AI tools to packaging and documentation workflows.
• Document findings, issues, and decisions clearly and proactively communicate blockers.

Skills

Chip design fundamentals

Design verification basics

Debugging complex systems

Tools

AI/LLM tooling

CI/CD pipelines

Job description

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our top leading semiconductor client. If you're interested and your experience matches the requirement, we'd love to hear from you.

Position: IP Packaging Engineer

Experience: 1-2 Years

Location: Hyderabad

Contract tenure: 1 year

Key Responsibilities

• Work onsite at Hyderabad as part of a distributed engineering team, collaborating closely with US-based counterparts on IP packaging deliverables
• Apply foundational knowledge of chip design and design verification (DV) concepts to properly package, validate, and release IP for downstream consumption
• Debug complex, multi-component systems including packaging pipelines, build flows, and design/verification environments - to isolate root causes and drive fixes
• Partner with design, DV, and build-system owners to understand IP requirements and ensure packaged deliverables meet quality and integration standards
• Identify opportunities to apply AI tools to streamline packaging, debugging, or documentation workflows
• Clearly document findings, issues, and packaging decisions, and communicate status and blockers proactively to stakeholders

Required Qualifications

• 1to 2 years of relevant professional experience in semiconductor design, verification, IP packaging, or related engineering domains
• Working understanding of chip design fundamentals and design verification (DV) basics (e.g., RTL concepts, testbenches, simulation flows)
• Demonstrated experience debugging complex systems (e.g., tracing failures across tools, scripts, or design/verification/packaging flows to root cause)

Preferred Qualifications (Big Plus)

• Understanding of hardware or software build systems (e.g., build orchestration, dependency management, CI/CD pipelines)
• Hands-on experience with AI models as a power user or developer (e.g., prompting/tool-building with LLMs, using AI coding assistants, or integrating AI into engineering workflows)