RTL Integration Engineer

Blueberry Semiconductors; Bengaluru; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Blueberry Semiconductors in Bengaluru seeks a highly experienced RTL Integra on Engineer to lead PCIe Gen5+ controller/PHY integration for advanced SoCs. You will own end-to-end RTL integration, ensure LTSSM compliance, and collaborate across DV, PHY, and firmware teams.

Expect deep PCIe protocol knowledge, hands-on silicon bring-up, and a focus on performance, latency and power across multiple traffic classes and chiplet-based designs.

Qualifications

• 5+ years of high-speed RTL integration experience preferred.
• Silicon-proven PCIe Gen5+ integration experience is mandatory.
• Exposure to PCIe Gen6/Gen7 is desirable.
• Experience with multi-die or chiplet SoCs is a plus.

Responsibilities

• Integrate PCIe Gen5+ controllers and PHYs into complex SoC architectures.
• Own end-to-end RTL integration including clocking, reset, and CSR.
• Ensure correct PCIe protocol LTSSM behavior across generations.
• Manage speed/width changes, recovery, and reset scenarios.
• Drive PIPE PHY interface integration with power-state and latency alignment.
• Implement robust error handling, replay logic, and AER paths.
• Optimize performance, latency, and power across traffic classes.
• Collaborate with DV, PHY, firmware, and software teams for bring-up.
• Support debug and silicon bring-up with instrumentation.

Skills

PCIe Gen5+ RTL

PCIe architecture

LTSSM states

TLP/DLLP formats

PIPE/PHY interface

Multi-clock CDC

ASPM L0s/L1

RAS/AER

PCIe on AXI/APB fabrics

Retimers

Post-silicon debug

Security concepts IDE protection

Job description

Role Overview

We are looking for a highly experienced RTL Integra on Engineer to lead PCIe Gen5 and beyond (Gen6/Gen7/Gen8) controller and PHY integration for advanced SoC and chiplet-based designs. The role requires deep PCIe protocol knowledge, strong RTL/SoC integration experience , and hands-on experience taking designs from integration through silicon bring-up readiness.

Key Responsibilities

• Integrate PCIe Gen5+ controllers and PHYs into complex SoC architectures
• Own end-to-end RTL integration, including parameteriza on, clocking, reset, and CSR integration
• Ensure correct implementaion on of PCIe protocol layers (TL/DL/PHY) and LTSSM behavior
• Manage speed and width change, recovery, and reset scenarios across generations
• Drive PIPE (4.x / 5.x) PHY interface integration, including power-state and latency alignment
• Implement robust error handling, replay logic support, and AER reporting paths
• Optimize performance, latency, and power across multiple VCs and traffic classes
• Collaborate with DV, PHY, firmware, and software teams to ensure compliance and bring-up readiness
• Support debug and silicon bring-up through visibility hooks and instrumentation.

Required Technical Skills

• Strong hands-on experience with PCIe Gen5 and above RTL integration
• Deep understanding of PCIe architecture (Root Complex, Endpoint, Switch)
• Expertise in LTSSM states, transitions, and recovery mechanisms
• Solid knowledge of TLP/DLLP formats, flow control, replay, and ordering rules
• Experience with PIPE interfaces and PHY interaction (rate/width change, power states)
• Proven skills in multi-clock design, CDC, and reset sequencing
• Familiarity with ASPM (L0s, L1, L1.1, L1.2) and low-power integration
• Strong understanding of error handling, RAS, and AER capability integration
• Experience integrating PCIe into AXI/APB-based SoC fabrics

Gen-Specific Expectations

• Gen5: 32 GT/s NRZ operation, tight timing margins, EQ awareness
• Gen6: FLIT-mode architecture, PAM4 signaling, FEC/CRC, PHY latency budge ng
• Gen7/Gen8: Scalable RTL, retimer/chiplet awareness, reliability and RAS focus

Experience & Qualifications

• 812+ years of experience in high-speed interface RTL integration
• Silicon-proven PCIe Gen5+ experience is mandatory
• Exposure to PCIe Gen6 FLIT-mode strongly preferred
• Experience with chiplet-based or multi-die SoCs is a plus

Preferred differentiators

• CXL 2.x / 3.x awareness
• Retimer/redriver integration exposure
• Post-silicon debug and bring-up experience
• Security concepts (IDE, link-level protection)