Principal PCIe Subsystem RTL lead

TYLsemi; India; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

TYLsemi in India is seeking a PCIe Sub-system Front-end RTL lead to own the microarchitecture from PHY to the Transaction Layer for high‑performance compute and AI silicon.

You will lead integration of third‑party PCIe controllers and PHY IP, define lane configurations, and drive verification with the DV team. This role partners with firmware and design teams to ensure timing, power, and production readiness.

Responsibilities

• Own the PCIe subsystem microarchitecture from the PHY interface through the MAC and Transaction Layer, defining the internal block boundaries, data paths, and control interfaces.
• Lead the integration of third-party PCIe controller and PHY hard IP, including wrapper RTL that adds mode selection, telemetry hooks, and bridging logic to the chiplet's internal fabric.
• Define and implement the bifurcation and lane-configuration logic, ensuring all supported lane-width configurations operate correctly across the full range of operating modes.
• Specify and drive implementation of the Transaction Layer pipeline: TLP reception, integrity checking, header classification, routing decisions, and handoff to downstream subsystems.
• Own the Virtual Channel and flow-control architecture, ensuring fair arbitration and back‑pressure handling across all traffic classes.
• Define the integration interface to the PCIe subsystem such asTLP-to-flit adaptation, flow‑control mapping, and error handling at the boundary.
• Collaborate with the management firmware team to define the PCIe register map, mode‑select interface, and run‑time telemetry structures exposed to the on‑chip management processor.
• Work with the Physical Design Lead to meet timing closure requirements for the PCIe subsystem, including MAC‑PHY interface timing, reset sequencing, and floorplan constraints.
• Hold the PCIe performance budget for each operating mode: bandwidth efficiency, latency through the Transaction Layer, and error recovery overhead.
• Define the PCIe power management architecture — link state transitions, ASPM policy, and integration with the chiplet‑level power coordination scheme.
• Lead PCIe silicon bring‑up planning: define bringup sequence, debug instrumentation requirements, loopback modes, and the hand‑off criteria for production readiness.
• Mentor and guide RTL design engineers responsible for PCIe subsystem implementation, providing architectural guidance and RTL review.
• Partner with the DV team to define the PCIe UVM verification plan, coverage model, and protocol‑checker requirements.
• Serve as the technical point of contact for PCIe‑related customer integration questions, supporting anchor

Job description

We are looking for a PCIe Sub-system Front-end RTL lead for next generation chiplet based SoCs for High-performance Compute and AI silicon .

What You’ll Do

• Own the PCIe subsystem microarchitecture from the PHY interface through the MAC and Transaction Layer, defining the internal block boundaries, data paths, and control interfaces.
• Lead the integration of third-party PCIe controller and PHY hard IP, including wrapper RTL that adds mode selection, telemetry hooks, and bridging logic to the chiplet's internal fabric.
• Define and implement the bifurcation and lane-configuration logic, ensuring all supported lane-width configurations operate correctly across the full range of operating modes.
• Specify and drive implementation of the Transaction Layer pipeline: TLP reception, integrity checking, header classification, routing decisions, and handoff to downstream subsystems.
• Own the Virtual Channel and flow-control architecture, ensuring fair arbitration and back‑pressure handling across all traffic classes.
• Define the integration interface to the PCIe subsystem such asTLP-to-flit adaptation, flow‑control mapping, and error handling at the boundary.
• Collaborate with the management firmware team to define the PCIe register map, mode‑select interface, and run‑time telemetry structures exposed to the on‑chip management processor.
• Work with the Physical Design Lead to meet timing closure requirements for the PCIe subsystem, including MAC‑PHY interface timing, reset sequencing, and floorplan constraints.
• Hold the PCIe performance budget for each operating mode: bandwidth efficiency, latency through the Transaction Layer, and error recovery overhead.
• Define the PCIe power management architecture — link state transitions, ASPM policy, and integration with the chiplet‑level power coordination scheme.
• Lead PCIe silicon bring‑up planning: define bringup sequence, debug instrumentation requirements, loopback modes, and the hand‑off criteria for production readiness.
• Mentor and guide RTL design engineers responsible for PCIe subsystem implementation, providing architectural guidance and RTL review.
• Partner with the DV team to define the PCIe UVM verification plan, coverage model, and protocol‑checker requirements.
• Serve as the technical point of contact for PCIe‑related customer integration questions, supporting anchor