ASIC Digital Design, Principal Engineer

Synopsys, Inc.; Bengaluru; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Synopsys in Bengaluru seeks a Principal ASIC Digital Design Engineer and PCIe technical authority. You will set architecture, write and review RTL, define micro-architecture, and drive design from concept to silicon-proven.

You will lead architecture reviews, mentor engineers, and collaborate with verification, PD, customers, and senior management to deliver high-speed IP such as PCIe Gen5/Gen6/Gen7, with CXL and related protocols.

Qualifications

• BSEE with 12+ years or MSEE with 10+ years.
• Proven principal/staff-plus leadership in ASIC digital design.
• Direct RTL ownership of complex, production digital designs.
• Deep PCIe controller/core design/architecture experience with CXL/AMBA/DDR/UCIe familiarity.
• Strong ASIC fundamentals: multi-clock design, CDC/RDC, resets, low power, DFT, timing-aware RTL.
• Experience with highly configurable/parameterized IP.
• Scripting for design automation (Python, TCL, Perl) is desirable.

Responsibilities

• Own PCIe digital architecture and RTL for major controller subsystems from micro-architecture to post-silicon support.
• Define micro-architecture, specifications, and implementation for high-performance PCIe IP.
• Document design decisions; act as authority for protocol, data-path, clocking/reset, and RAS issues.
• Hands-on RTL development and complex debug (simulation, formal, emulation, silicon).
• Raise design quality through reviews, CDC/RDC discipline, and maintainable RTL across a large parameterized codebase.
• Collaborate with verification, formal, emulation, PD, firmware, and system teams for silicon success.
• Influence PCIe IP strategy, roadmap, and next-gen architecture including CXL and variants.
• Communicate status, risk, and trade-offs to senior management, architects, and customers.

Skills

PCIe architecture

RTL ownership

ASIC digital design

Multi-clock design

CDC/RDC

DFT

Python/TCL/Perl scripting

AMS/AMBA/CXL/DDR/UCIe familiarity

Education

BSEE with 12+ years or MSEE with 10+ years

Tools

Python

TCL

Perl

Scripting for design automation

Job description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence—from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to help transform the future through continuous technological innovation.

You Are:

You are a Principal ASIC Digital Design Engineer and a recognized PCIe technical authority. You set architecture and write and review RTL. You define micro-architecture, make trade-offs across performance, power, area, and configurability, and stay in the design until the IP is silicon-proven.

You have shipped complex, highly parameterized high-speed interface IP. You are fluent in PCIe (Gen5/Gen6/Gen7) digital design—transaction layer, data path, link/controller functions, RAS, and power management—and you have working knowledge of adjacent protocols such as CXL, AMBA, DDR, or UCIe.

You lead through architecture, design reviews, and direct technical engagement. You mentor senior and staff engineers, resolve complex issues, and represent the design in reviews with verification, physical design, customers, and senior management.

What You'll Be Doing:

• Own PCIe digital architecture and RTL for major controller subsystems, from micro-architecture through design convergence and post-silicon support.
• Define micro-architecture, design specifications, and implementation approach for high-performance, low-power, scalable, configurable PCIe IP.
• Make and document key design decisions; act as the go-to authority for protocol, data-path, clocking/reset, and RAS issues.
• Hands-on RTL development: implement critical paths, review detailed design, and drive complex debug (simulation, formal, emulation, and silicon).
• Raise design quality bar through reviews, coding standards, CDC/RDC discipline, and RTL maintainability across a large parameterized codebase.
• Work with verification, formal, emulation, physical design, firmware, and system teams to get IP integrated and silicon-successful.
• Influence PCIe IP technical strategy, roadmap, and next-generation architecture, including CXL and automotive variants.
• Communicate status, technical risk, and trade-offs to senior management, architects, and customers.

The Impact You Will Have:

• Deliver industry-leading PCIe digital IP used by leading commercial, enterprise, and automotive customers.
• Improve architectural quality, predictability, and execution on current and next-generation cores.
• Raise the technical bar across the design team through architecture leadership and mentorship.
• Strengthen Synopsys’ leadership position in high-speed interface IP.

What You'll Need:

• BSEE with 12+ years of relevant experience, or MSEE with 10+ years.
• Demonstrated Principal / Staff-plus technical leadership in ASIC digital design
• Direct RTL ownership of complex, production digital designs
• Deep PCIe controller/core digital design and architecture experience, CXL, AMBA, DDR, UCIe, or similar protocols strongly desired.
• Proven ability to define micro-architecture and take designs from concept through silicon.
• Strong ASIC fundamentals: multi-clock design, CDC/RDC, resets, low power, DFT, synthesizable RTL, and timing-aware design.
• Experience with highly configurable / parameterized IP is strongly desired.
• Scripting for design automation (Python, TCL, Perl) is desirable. Familiarity with AI-assisted design tools and flows is a plus.

Who You Are:

• A hands-on PCIe architect who leads by example in the RTL.
• Decisive on technical trade-offs; calm on the hardest debugs.
• A clear communicator across design, verification, PD, and customers.
• A mentor who multiplies the team and can create other technical leaders