Principal PCIe RTL Engineer

Mulya Technologies; India; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Mulya Technologies seeks a PCIe Sub-system Front-end RTL Lead for next-gen chiplet-based SoCs. You will own the PCIe sub-system architecture from PHY to MAC and TL, defining internal blocks, data paths and interfaces.

You will lead integration of PCIe hard IP, manage lane configuration across modes, and drive the TL pipeline, VP, and error handling. You will mentor RTL engineers and collaborate with firmware and DV teams.

Qualifications

• 10-15 years of digital IC design experience with at least 4 years in PCIe subsystem design or integration.
• Hands-on experience with PCIe hard IP integration, wrapper RTL, and PnR constraints.
• Strong SystemVerilog RTL skills and multi-clock-domain design proficiency.
• Familiarity with SR-IOV, PCIe power management, and PCIe protocol handling.

Responsibilities

• Own the PCIe subsystem microarchitecture from PHY to transaction layer and control interfaces.
• Lead integration of third-party PCIe controller and PHY hard IP and wrapper RTL.
• Define lane-configuration and TLP pipeline, including fault handling and error reporting.
• Own Virtual Channel and flow-control architecture across traffic classes.
• Define integration interfaces and run-time telemetry with on-chip management.
• Mentor RTL engineers and define PCIe UVM verification plan with coverage.

Skills

PCIe architecture

SystemVerilog RTL

RTL design leadership

Multi-clock-domain design

UVM verification

PCIe IP integration

CXL protocol knowledge

Education

BS/MS in Electrical/Electronic Engineering

Tools

UVM

Verilog/SystemVerilog

Job description

We are looking for a PCIe Sub-system Front-end RTL lead for next generation chiplet based SoCs for High-performance Compute and AI silicon .

What You’ll Do

• Own the PCIe subsystem microarchitecture from the PHY interface through the MAC and Transaction Layer, defining the internal block boundaries, data paths, and control interfaces.
• Lead the integration of third-party PCIe controller and PHY hard IP, including wrapper RTL that adds mode selection, telemetry hooks, and bridging logic to the chiplet's internal fabric.
• Define and implement the bifurcation and lane-configuration logic, ensuring all supported lane-width configurations operate correctly across the full range of operating modes.
• Specify and drive implementation of the Transaction Layer pipeline: TLP reception, integrity checking, header classification, routing decisions, and handoff to downstream subsystems.
• Own the Virtual Channel and flow-control architecture, ensuring fair arbitration and back-pressure handling across all traffic classes.
• Define the integration interface to the PCIe subsystem such asTLP-to-flit adaptation, flow-control mapping, and error handling at the boundary.
• Collaborate with the management firmware team to define the PCIe register map, mode-select interface, and run-time telemetry structures exposed to the on-chip management processor.
• Work with the Physical Design Lead to meet timing closure requirements for the PCIe subsystem, including MAC-PHY interface timing, reset sequencing, and floorplan constraints.
• Hold the PCIe performance budget for each operating mode: bandwidth efficiency, latency through the Transaction Layer, and error recovery overhead.
• Define the PCIe power management architecture - link state transitions, ASPM policy, and integration with the chiplet-level power coordination scheme.
• Lead PCIe silicon bring-up planning: define bringup sequence, debug instrumentation requirements, loopback modes, and the hand-off criteria for production readiness.
• Mentor and guide RTL design engineers responsible for PCIe subsystem implementation, providing architectural guidance and RTL review.
• Partner with the DV team to define the PCIe UVM verification plan, coverage model, and protocol-checker requirements.
• Serve as the technical point of contact for PCIe-related customer integration questions, supporting anchor customer engagements on interface bring-up and interoperability.
• Author and maintain the PCIe subsystem micro-architecture specification, keeping it current through RTL implementation and sign-off.

What We’re Looking For

• 10-15 years of digital IC design experience, with at least 4 years focused on PCIe subsystem design or integration at the block-lead or module-owner level.
• Deep expertise in PCIe architecture: Transaction Layer, Data Link Layer, Physical Layer, TLP structure, flow control, Virtual Channels, and error handling.
• Hands-on experience integrating PCIe hard IP (controller and/or SerDes PHY) into production SoC or chiplet designs, including wrapper RTL, reset sequencing, and PnR constraints.
• Background in SR-IOV, multi-function device configuration, or host software driver interaction at the hardware level.
• Strong SystemVerilog RTL skills: able to write, review, and own production RTL for complex pipelined state machines, FIFOs, arbiters, and control logic.
• CXL 1.1/2.0 or 3.0 protocol knowledge, particularly CXL.io and CXL.mem transaction handling built on the PCIe fabric.
• Solid understanding of PCIe PHY-MAC interface protocols and timing requirements,
• Experience with PCIe compliance testing and PCI-SIG certification process - understanding of test requirements, common failure modes, and debug methodology.
• Familiarity with PCIe power management, L0s/L1 state machines, state transitions etc.
• Competency in multi-clock-domain design: async FIFO, CDC synchronizers, and clock crossing at the PCIe-to-internal-fabric boundary.
• BS/MS in Electrical Engineering, Computer Engineering, or equivalent.

Good To Have

• Experience with UCIe or another die-to-die protocol at the PCIe TLP adaptation layer - mapping TLPs to a flit-based D2D transport.
• Prior experience with protocol bridging or gearbox designs that span multiple PCIe generations.
• Familiarity with PCIe IP integration, including customization and support engagement.
• Experience at an advanced-node (7 nm or below) tape-out, particularly with the timing closure and floorplan considerations for designs.