PCIe IP Validation Engineer

Capgemini Engineering; Bengaluru; Vor Ort; INR 4.000.000 - 7.000.000; Vollzeit

Zusammenfassung

Capgemini Engineering is seeking an experienced Post-Silicon Validation Engineer specializing in PCIe technologies to transition next-generation silicon from fab to production, debugging complex hardware bugs and validating electrical and protocol compliance.

You will lead bring-up on reference boards, drive test strategies, and automate validation workflows across PVT, collaborating with software and OS teams to ensure robust PCIe IP performance.

Qualifikationen

• 8+ years in hardware validation and lab debugging.
• Experience with PCIe protocol standards (Gen4/5/6) and LTSSM.
• Hands-on with high-speed lab equipment and automated validation frameworks.

Aufgaben

• Define post-silicon validation plans, test strategies and coverage goals for the PCIe subsystem.
• Lead first-silicon bring-up, initial power-on phases and functional health checks for the PCIe IP block.
• Triage and isolate hardware, firmware and software integration issues across PCIe layers (Physical, Data Link, Transaction).
• Execute and automate PCIe compliance test suites (PCI-SIG Gold Suite) for certification.
• Use lab gear to diagnose signal integrity and LTSSM issues.
• Build and maintain automated validation frameworks to scale test execution across PVT corners.

Kenntnisse

Hardware validation

Debugging

Python scripting

C/C++

OS knowledge

Test automation

Ausbildung

B.Tech/M.Tech in Electronics/Electrical/Computer Engineering

Tools

Oscilloscopes

Protocol Analyzers

BERT systems

LTSSM analysis

PCIe compliance tools

Jobbeschreibung

We are seeking an experienced Post-Silicon Validation Engineer specializing in PCI Express (PCIe) technologies. In this role, you will transition next-generation silicon from the fab to production. You will debug complex hardware bugs, validate electrical and protocol compliance, and test PCIe IP performance in physical system environments.

Key Responsibilities:

• Validation Strategy: Define post-silicon validation plans, test strategies, and coverage goals for the PCIe subsystem on reference boards and customer platforms.
• Silicon Bring-Up: Lead first-silicon bring-up, initial power-on phases, and functional health checks for the PCIe IP block.
• Protocol Debugging: Triage and isolate hardware, firmware, and software integration issues across all PCIe layers (Physical, Data Link, and Transaction).
• Compliance Testing: Execute and automate official PCIe compliance test suites (e.g., PCI-SIG Gold Suite) to ensure formal industry certification.
• Lab Execution: Use high-speed lab equipment to diagnose signal integrity and link training (LTSSM) issues.
• Expertise in RAS feature set along with good exposure on x86 architecture
• Automation Development: Build and maintain automated validation frameworks to scale test execution over variable PVT (Process, Voltage, Temperature) corners.
• Exposure to RDMA or similar technologies is a plus

Preferred Qualifications & Skills:

• Education: B.Tech/M.Tech in Electronics, Electrical, or Computer Engineering.
• Experience: 8+ to 12+ years of hardware validation and lab debugging experience.
• Lab Equipment: Hands-on mastery of high-speed Oscilloscopes, Protocol Analyzers (Teledyne LeCroy, VIAVI), and BERT systems.
• Domain Knowledge: Deep understanding of PCIe protocol standards (Gen 4, Gen 5, or Gen 6), LTSSM, and equalization phases.
• OS & Drivers: Strong understanding of Linux/Windows OS kernels, device driver interactions, and PCIe memory mapping (MMIO, DMA).
• Scripting: Proficiency in Python or C/C++ for test script automation and hardware register manipulation.