Technical Lead-Design Verification

eInfochips (An Arrow Company); Bengaluru; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

eInfochips (An Arrow Company) in Bengaluru is seeking a Technical Lead for ASIC Design Verification to drive verification strategy and oversee a mid‑sized team.

The role demands hands‑on SystemVerilog HVL, UVM‑based verification, and experience leading 10+ engineers across multiple projects with customer interaction.

Qualifications

• Minimum 8 years of experience in SystemVerilog HVL.
• 8+ years in OVM/UVM/VMM/Test Harness.
• Hands-on experience with assertions, checkers, coverage.
• Led at least 2–3 SoC verification projects.
• Experience in test/coverage and verification environments.
• Knowledge of Ethernet, PCIe, MIPI, USB or similar protocols.
• Experience leading 5–10 engineers.

Responsibilities

• Architect verification environment for ASIC SoC and provide verification support from planning to customer deliveries.
• Lead an IP Verification team and provide technical leadership to the Design Verification group.
• Lead a team of 10–13 engineers.
• Coach and mentor team members and plan careers.
• Lead management and customer reviews for multiple projects.
• Define and maintain end-to-end formal verification flow.
• Develop/modify scripts to automate the verification process.
• Maintain and extend assertion libraries for simulation and FV.
• Develop verification environment including assumptions, assertions, and cover properties.

Skills

SystemVerilog HVL

OVM/UVM/Test Harness

Assertion development

Test and coverage planning

Team leadership

SoC verification

Education

BE/B.Tech/M.E./M.Tech in VLSI/Electronics/Electrical/CS/Instrumentation

Job description

POSITION TITLE: Technical Lead – ASIC Design Verification

POSITION SUMMARY

The candidate should have direct and first‑hand experience working in managing 4 -10 member engineering team – and servicing clients in Project (ODC) based execution model as well as Staffing (Hyderabad Onsite requirements).

ROLE & RESPONSIBILITIES

• Incumbent will be responsible for Architecting Verification Environment for ASIC SoC and providing verification support from defining verification plan to various customers products
• Incumbent will lead of an IP Verification team and provide technical leadership to the Design Verification team as a whole
• To lead a team of 10-13 engineers
• Effectively manage team members through coaching and mentoring and provide guidance and career planning to team-members.
• Must lead management and customer reviews for multiple projects
• The specification, implementation, and maintenance of an integrated end-to-end formal verification flow for the formal verification objective.
• Develop/modify scripts to automate the verification process.
• Maintain and extend assertion libraries, including support for both simulation and FV.
• Developing verification environment including environment assumptions, assertions, and cover properties in context of the verification plan

ESSENTIAL SKILLS & EXPERIENCE

• Minimum 8 years of experience in System Verilog HVL.
• Minimum 8 year of experience in OVM/UVM/VMM/Test Harness.
• Hands on experience of developing assertion, checkers, coverage and scenario creation.
• Must have executed at-least 2 to 3 SoC Verification projects
• Experience in developing test and coverage plan, Verification environment and validation plan.
• Knowledge of at-least one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is required.
• Review and Audit participation.
• At-least 1 years of experience in handling team of 5 to 10 engineers.
• Define/derive Scope, Estimation, Schedule and Deliverables of proposed work.
• Assure compatibility of resources, tools, platform
• Work with customers through acceptance of deliverables.
• Effectively manage team members through coaching and mentoring and provide guidance and career planning to team-members.

EDUCATION BACKGROUND

• B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering.