RTL Design - Microarchitecture

Rozgoo; India; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

Rozgoo in India is seeking an ASIC Design Engineer to define microarchitecture, RTL, and high-speed interface IPs for high-performance, power-efficient silicon solutions.

You will collaborate with cross-functional teams to deliver scalable ASIC SoCs, targeting PCIe Gen4/5, 100G/400G Ethernet, USB3/4, and SerDes interfaces. Ten years of experience in ASIC/SoC design is expected, with strong RTL and microarchitecture expertise.

Qualifications

• Minimum 10 years of ASIC/SoC design experience.
• Strong RTL design and microarchitecture skills.
• Experience with PCIe Gen4/5, Ethernet 100G/400G is a plus.

Responsibilities

• Define microarchitecture and RTL for high‑speed interface IPs.
• Collaborate with cross-functional teams to deliver high-performance silicon solutions.

Skills

ASIC design

RTL design

Microarchitecture

High-speed interfaces

PCIe Gen4/5

Ethernet 100G/400G

Job description

Role Overview:

As an ASIC Design Engineer, you will play a key role in microarchitecture definition, RTL design, and implementation of high-speed interface IPs. You will collaborate with cross-functional teams to deliver high-performance, power-efficient, and scalable silicon solutions.

Key Responsibilities:

Experience 10yrs , Bangalore location Architect and design high-performance ASIC SoCs, targeting high-speed protocols such as PCIe Gen4/5, 100G/400G Ethernet, USB3/4, SerDes-based interface…