SOC Design Lead & Micro-Architect – High-Speed interface Subsystems

7Rays Semiconductors; Bengaluru; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

7Rays Semiconductors is seeking an experienced Micro-Architect & Design Lead to drive architecture and RTL implementation for high-speed subsystems. The role requires hands-on micro-architecture skills and expertise in PCIe Gen6/7, HBM3/4, Ethernet, or UCIe, with exposure to additional domains as a plus.

The candidate will define micro-architecture, develop RTL with lint/CDC/RDC checks, own subsystem designs, and collaborate with verification and PD teams to meet performance, power, and timing

Qualifications

• 10–15 years of experience in micro-architecture and RTL design.
• Hands-on design in PCIe Gen6/7, HBM3/4, Ethernet or UCIe.

Responsibilities

• Define detailed micro-architecture, design specs, timing diagrams and performance models.
• Develop RTL (Verilog/SystemVerilog) with lint, CDC/RDC, and synthesis in mind.
• Own subsystem design/integration for PCIe Gen6/7, HBM3/4, Ultra Ethernet or UAL, or UCIe/BOW.
• Collaborate with verification and PD teams to meet performance, power and timing goals.
• Support debug across simulation, emulation and silicon bring-up.
• Lead and mentor a small team, review designs and drive technical decisions.

Skills

Micro-architecture

RTL design

High-speed interfaces

Leadership

Tools

Verilog/SystemVerilog

Synthesis

CDC/RDC

AXI/CHI interconnects

Job description

At 7Rays Semiconductors (https://7rayssemi.com/), we provide end-to-end VLSI design solutions to help our clients achieve execution excellence. Our team of experts specializes in architecture, RTL design, verification, validation, physical design, implementation, and post-silicon validation using the latest technologies and methodologies.

We work closely with our clients, building effective partnerships to deliver high-quality solutions tailored to their needs. With a proven track record of successful projects, we are committed to excellence and innovation in semiconductor design.

Job Title: Micro-Architect & Design Lead – High-Speed interface Subsystems

Experience: 10–15 years

Skills:

Micro-architecture, RTL design, high-speed interfaces (ANY ONE of PCIe Gen6 / HBM3 / Ethernet / UCIe)

About the Role

We are looking for an experienced Micro-Architect & Design Engineer to drive architecture and RTL implementation of high-performance subsystems. Candidates must have strong micro-architecture skills and hands-on design experience in at least one of the following domains: PCIe, HBM, Ethernet, or UCIe. Exposure to others is a plus.

Key Responsibilities

• Define detailed micro-architecture, design specs, timing diagrams, and performance models.
• Develop high-quality RTL (Verilog/SystemVerilog) ensuring clean lint, CDC/RDC, and synthesis outcomes.
• Own subsystem design/integration for PCIe Gen6/7, HBM3/4, Ultra Ethernet or UAL, or UCIe / BOW.
• Work with verification and PD teams to meet performance, power, and timing goals.
• Support debug across simulation, emulation, and silicon bring-up.
• Lead and mentor a small team, review designs, and drive technical decisions.

Required Skills

• Strong fundamentals in micro-architecture: pipelines, FIFOs, arbitration, datapath & control logic.
• Hands-on experience in at least one:
• PCIe Gen6 or Gen7
• HBM3 or HBM4
• Ultra Ethernet or UAL
• Solid understanding of AXI/CHI interconnects, SoC/IP integration, clock/reset design, CDC/RDC, synthesis, and STA.
• Proven ability to lead, mentor, and guide engineering teams.

Good to Have

• Experience with NoC, DMA, memory pipelines, or chiplet-based SoC architectures.
• Ability to collaborate across multi-site and cross-functional teams.
• Hands-on experience with Synopsys Interface IPs (PCIe, HBM, Ethernet, UCIe, etc.)