ASIC / RTL Design Lead

SmartSoC Solutions Pvt Ltd; Bengaluru; Presencial; INR 4 000 000 - 6 000 000; Tempo integral

Resumo da oferta

SmartSoC Solutions Pvt Ltd is seeking an experienced RTL Design Lead with 10+ years in RTL design, microarchitecture, and SoC development. You will lead RTL activities from specification to silicon-ready implementation, focusing on CDC flow, SerDes, PCIe, and firmware integration.

You will collaborate with firmware teams and design verification to ensure RTL quality, timing, and successful design closure across IP/SoC levels. Mentorship and cross-functional coordination are key parts of the role.

Qualificações

• 10+ years in RTL design and SoC development.
• Strong proficiency in Verilog/SystemVerilog and synthesizable RTL coding.
• Hands-on CDC analysis, synchronization techniques, and metastability concepts.
• Understanding of SerDes and high-speed interface architecture.
• Experience with hardware-firmware interaction, memory-mapped registers, and initialization flows.
• Familiarity with lint, CDC tools, synthesis, timing analysis, and RTL sign-off.

Responsabilidades

• Lead RTL design and development for complex IPs and SoC subsystems using Verilog/SystemVerilog.
• Define and review microarchitecture, RTL specifications, design plans, and implementation strategies.
• Drive Clock Domain Crossing (CDC) flow, including analysis and synchronization techniques.
• Work on high-speed interfaces involving SerDes and PCIe, including protocol understanding and integration.
• Collaborate with firmware and embedded software teams for hardware-firmware integration and system bring-up.
• Ensure RTL quality through lint checks, CDC verification, synthesis readiness, and timing considerations.
• Debug RTL and integration issues and perform root-cause analysis across IP/SoC levels.
• Coordinate with Design Verification teams to define strategies and achieve design closure.
• Collaborate with Physical Design teams to address timing, power, area, and RTL implementation challenges.
• Mentor RTL engineers, review deliverables, and establish coding standards.
• Own design milestones, technical deliverables, and cross-functional issue resolution.

Conhecimentos

RTL Design

CDC Flow

SerDes

PCIe

Firmware integration

Design Quality

EDA Tools

Ferramentas

Verilog/SystemVerilog

Descrição da oferta de emprego

SmartSoC Solutions is looking for an experienced and technically strong RTL Design Lead with 10+ years of experience in RTL design, microarchitecture, and SoC development. The ideal candidate should have strong expertise in CDC Flow, SerDes, PCIe, AXI protocols, and Firmware integration, along with proven experience leading RTL design activities from specification to silicon-ready implementation.

Key Responsibilities:

• Lead RTL design and development for complex IPs and SoC subsystems using Verilog/System Verilog.
• Define and review microarchitecture, RTL specifications, design plans, and implementation strategies.
• Drive Clock Domain Crossing (CDC) flow, including CDC analysis, synchronization techniques, and resolution of clock-domain-related issues.
• Work on high-speed interface designs involving SerDes and PCIe, including protocol-level understanding and interface integration.
• Collaborate with firmware and embedded software teams to support hardware-firmware integration, register mapping, initialization sequences, and system bring-up.
• Ensure RTL quality through lint analysis, CDC checks, synthesis readiness, timing considerations, and design reviews.
• Debug complex RTL and integration issues and drive root-cause analysis across IP and SoC levels.
• Work closely with Design Verification teams to define verification strategies, resolve functional issues, and achieve design closure.
• Coordinate with Physical Design teams to address timing, power, area, and RTL implementation challenges.
• Mentor RTL engineers, review design deliverables, and establish coding standards and best practices.
• Own design milestones, technical deliverables, and cross-functional issue resolution.

Required Technical Skills:

• Experience: 10+ years in RTL design and SoC development, with demonstrated technical leadership experience.
• RTL Design: Strong proficiency in Verilog/System Verilog, synthesizable RTL coding, and microarchitecture development.
• CDC Flow: Hands-on experience with CDC analysis, synchronizer design, metastability concepts, reset-domain considerations, and CDC violation debugging.
• SerDes: Understanding of high-speed serial interface architecture, data-path design, and SerDes subsystem integration.
• Firmware: Understanding of hardware-firmware interaction, memory-mapped registers, interrupt mechanisms, initialization flows, and debugging during system integration.
• Design Quality: Experience with lint, CDC tools, synthesis, timing analysis fundamentals, and RTL sign-off activities.
• Tools: Familiarity with industry-standard EDA tools for RTL simulation, lint, CDC, synthesis, and design analysis.