RTL Design Engineer

ACL Digital; Chennai District; On-site; INR 600,000 - 1,000,000; Full time

Job summary

A leading technology company in Chennai is looking for expertise in VLSI/Semiconductors. The role involves designing and implementing RTL for wireless modem IPs and SoC subsystems. Ideal candidates will have 1-3 years of experience in digital front-end ASIC/RTL design with expertise in Verilog/SystemVerilog. This is a full-time position at an innovative digital and systems engineering partner.

Qualifications

• 1–3 years of experience in digital front-end ASIC/RTL design.
• Strong expertise in Verilog/SystemVerilog RTL coding and micro-architecture development.
• Familiarity with wireless protocols such as IEEE 802.11, LTE, or 5G NR.
• Solid understanding of bus protocols and bridge logic.

Responsibilities

• Design and implement RTL for wireless modem IPs and SoC subsystems.
• Develop specifications and deliver high-quality, synthesizable RTL.
• Integrate complex subsystems and support design convergence.
• Analyze and optimize for performance, area, and power.

Skills

Verilog/SystemVerilog

Digital front-end ASIC/RTL design

Wireless protocols (IEEE 802.11, LTE, 5G)

Bus protocols (AXI, AHB, APB)

Low-power design methodologies

Post-silicon debug

Documentation skills

Communication skills

Tools

Spyglass

Design Compiler

PrimeTime

Job description

Direct message the job poster from ACL Digital

Hiring Expertise/ Leaders for VLSI/ Semiconductors!

Experience: 1 to 3 Years

Job Description

Job Role:

• Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog.
• Develop micro-architecture specifications and deliver high-quality, synthesizable RTL.
• Integrate complex subsystems into SoC environments and support design convergence.
• Collaborate with system architects, verification, SoC, software, DFT, and physical design teams.
• Apply low-power design techniques including clock gating, power gating, and multi-voltage domains.
• Analyze and optimize for performance, area, and power.
• Ensure protocol compliance and performance of interconnects, buses (AXI, AHB, APB), and bridges.
• Conduct CDC and lint checks using tools like Spyglass and resolve waivers.
• Participate in post-silicon debug and bring-up activities.

Job Qualification

• 1–3 years of experience in digital front-end ASIC/RTL design.
• Strong expertise in Verilog/SystemVerilog RTL coding and micro-architecture development.
• Familiarity with wireless protocols such as IEEE 802.11 (a/b/g/n/ac/ax/be), LTE, or 5G NR is highly desirable.
• Solid understanding of bus protocols (AXI, AHB, APB) and bridge logic.
• Experience with wireless modem IPs or similar high-performance digital blocks is a plus.
• Familiarity with low-power design methodologies and CDC handling.
• Hands-on experience with tools like Spyglass, 0-in, Design Compiler, PrimeTime, and simulation environments.
• Exposure to post-silicon debug and SoC integration challenges.
• Strong documentation and communication skills.
• Self-motivated with a collaborative mindset and ability to work with minimal supervision.

About Company

ACL Digital, part of the ALTEN Group, is a trusted AI-led, Digital & Systems Engineering Partner driving innovation by designing and building intelligent systems across the full technology stack — from chip to cloud. By integrating AI and data-powered solutions, we help enterprises accelerate digital transformation, optimize operations, and achieve scalable business outcomes. Partner with us to turn complexity into clarity and shape the future of your organization.

Seniority level

Associate

Employment type

Full-time

Job function

Semiconductor Manufacturing

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