Design Verification Engineer

ACL Digital; Hyderabad; On-site; INR 800,000 - 1,200,000; Full time

Job summary

A leading technology firm is looking for an HR Executive TAG to recruit DV/RTL/DFT/AL/ALD/PD Engineers in Hyderabad. The ideal candidate should have 5–7 years of experience with strong expertise in SystemVerilog UVM and related tools. This full-time position offers the opportunity to work in semiconductor manufacturing at a mid-senior level.

Qualifications

• 5–7 years of experience required.
• Hands-on expertise in multi-master/multi-slave configurations is a plus.
• Experience with DRAM memory controllers, traffic patterns, bandwidth & latency analysis is a plus.

Responsibilities

• Conduct recruitment for DV/RTL/DFT/AL/ALD/PD Engineers.
• Verify and validate hardware design based on industry standards.
• Work closely with engineering teams to ensure smooth recruitment cycles.

Skills

SystemVerilog UVM

AXI4

NoC protocols

VCS

Questa

Xcelium

Riviera

Vivado

Job description

HR Executive TAG at ACL Digital (VLSI Recruiter)

Hiring For DV/RTL/DFT/AL/ALD/PD Engineers – Contact: [e-mail]

• Strong SystemVerilog UVM, behavioral modeling, and system-level performance verification experience.
• Hands‑on expertise in AXI4, NoC protocols, and multi‑master/multi‑slave configurations.
• Experience with DRAM memory controllers, traffic patterns, bandwidth & latency analysis is a plus.
• Proficiency with VCS/Questa/Xcelium/Riviera and Vivado debug is essential.

Experience: 5–7 years

Notice Period: 0–30 days

Seniority Level

Mid‑Senior level

Employment Type

Full‑time

Job Function

Semiconductor Manufacturing

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