RTL Design Engineer

Nsemi Design Services India Pvt Ltd; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Nsemi is seeking an RTL Design Engineer to develop high-performance digital circuits through RTL design. You will design, model, and verify RTL code using VHDL or Verilog to create efficient systems.

You will collaborate with cross-functional teams to meet stringent performance, power, and area targets, with a focus on quality and innovation.

Qualifications

• Typically requires minimum of 3+ years of experience in System Verilog, UVM.
• Bachelor's OR Master’s Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering.

Responsibilities

• Design, model, and verify RTL code to create efficient and reliable digital systems.
• Collaborate with cross-functional teams to ensure designs meet performance, power, and area specifications.
• Develop testbenches and verification components using System Verilog UVM libraries.
• Break down RTL modules and verify them with UVM-based test environments.

Skills

SystemVerilog

UVM

C/C++

SystemC

RTL

Education

Bachelor's or Master’s Degree in Electronics or Electrical or Telecom or VLSI Engineering

Tools

VHDL

Verilog

RTL

UVM

Job description

As an RTL Design Engineer at Nsemi, you will play a pivotal role in developing high-performance digital circuits through Register Transfer Level (RTL) design. Your responsibilities will include designing, modeling, and verifying RTL code using VHDL or Verilog to create efficient and reliable digital systems. You will collaborate with cross-functional teams to ensure that your designs meet stringent performance, power, and area specifications. This role requires a strong understanding of digital logic, excellent problem-solving skills, and a commitment to quality and innovation.

RTL Design Engineer

As an RTL Design Engineer at Nsemi, you will play a pivotal role in developing high-performance digital circuits through Register Transfer Level (RTL) design. Your responsibilities will include designing, modeling, and verifying RTL code using VHDL or Verilog to create efficient and reliable digital systems. You will collaborate with cross-functional teams to ensure that your designs meet stringent performance, power, and area specifications. This role requires a strong understanding of digital logic, excellent problem-solving skills, and a commitment to quality and innovation.

RTL Design Engineer

As an RTL Design Engineer at Nsemi, you will play a pivotal role in developing high-performance digital circuits through Register Transfer Level (RTL) design. Your responsibilities will include designing, modeling, and verifying RTL code using VHDL or Verilog to create efficient and reliable digital systems. You will collaborate with cross-functional teams to ensure that your designs meet stringent performance, power, and area specifications. This role requires a strong understanding of digital logic, excellent problem-solving skills, and a commitment to quality and innovation.

RTL Design Engineer

Qualification Required

• Typically requires minimum of 3+ years of experience in System Verilog, UVM.
• Bachelors OR Master’s Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering.
• Typically requires minimum of 3+ years of experience in System Verilog, UVM.
• Bachelors OR Master’s Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering.

Qualification Required

• Typically requires minimum of 3+ years of experience in System Verilog, UVM.
• Bachelors OR Master’s Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering.
• Typically requires minimum of 3+ years of experience in System Verilog, UVM.
• Bachelors OR Master’s Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering.

Roles And Responsibilities

• As a member of the design verification team, it is your job to break things. You will work with logic designers to test RTL modules using UVM and will have the opportunity to develop re-usable verification components and testbenches.
• If you thrive in a collaborative environment (even while social distancing) and enjoy learning new techniques and approaches for verification and tooling while working on machine learning acceleration hardware for Azure, then this is the position for you. Responsible for the on-time delivery of block-level layouts, with acceptable quality.
• You will develop testbench components and stimulus using System Verilog UVM libraries. On a small, agile team, you will start from microarchitectural specifications and develop test environments and test plans to achieve code coverage targets. You will collaborate via design reviews and code reviews.
• As a member of the design verification team, it is your job to break things. You will work with logic designers to test RTL modules using UVM and will have the opportunity to develop re-usable verification components and testbenches.
• If you thrive in a collaborative environment (even while social distancing) and enjoy learning new techniques and approaches for verification and tooling while working on machine learning acceleration hardware for Azure, then this is the position for you. Responsible for the on-time delivery of block-level layouts, with acceptable quality.
• You will develop testbench components and stimulus using System Verilog UVM libraries. On a small, agile team, you will start from microarchitectural specifications and develop test environments and test plans to achieve code coverage targets. You will collaborate via design reviews and code reviews.

Roles And Responsibilities

• As a member of the design verification team, it is your job to break things. You will work with logic designers to test RTL modules using UVM and will have the opportunity to develop re-usable verification components and testbenches.
• If you thrive in a collaborative environment (even while social distancing) and enjoy learning new techniques and approaches for verification and tooling while working on machine learning acceleration hardware for Azure, then this is the position for you. Responsible for the on-time delivery of block-level layouts, with acceptable quality.
• You will develop testbench components and stimulus using System Verilog UVM libraries. On a small, agile team, you will start from microarchitectural specifications and develop test environments and test plans to achieve code coverage targets. You will collaborate via design reviews and code reviews.
• As a member of the design verification team, it is your job to break things. You will work with logic designers to test RTL modules using UVM and will have the opportunity to develop re-usable verification components and testbenches.
• If you thrive in a collaborative environment (even while social distancing) and enjoy learning new techniques and approaches for verification and tooling while working on machine learning acceleration hardware for Azure, then this is the position for you. Responsible for the on-time delivery of block-level layouts, with acceptable quality.
• You will develop testbench components and stimulus using System Verilog UVM libraries. On a small, agile team, you will start from microarchitectural specifications and develop test environments and test plans to achieve code coverage targets. You will collaborate via design reviews and code reviews.

Required Technical And Professional Expertise

• Strong knowledge Design & Verification methodologies of either of these (Times/Untimed SW Models), RTL IP, VIPs, UVM Env.
• Understanding of verification tools like Simulator, Synthesis etc.
• Hands on experience on C/C++, System Verilog, UVM, SystemC, RTL
• Understanding of some of the standard protocol interfaces like AMBA, Automotive, PCIe, USB etc.
• Excellent written and verbal interpersonal skills
• Self-motivated and great teammate
• Strong knowledge Design & Verification methodologies of either of these (Times/Untimed SW Models), RTL IP, VIPs, UVM Env.
• Understanding of verification tools like Simulator, Synthesis etc.
• Hands on experience on C/C++, System Verilog, UVM, SystemC, RTL
• Understanding of some of the standard protocol interfaces like AMBA, Automotive, PCIe, USB etc.
• Excellent written and verbal interpersonal skills
• Self-motivated and great teammate

Required Technical And Professional Expertise

• Strong knowledge Design & Verification methodologies of either of these (Times/Untimed SW Models), RTL IP, VIPs, UVM Env.
• Understanding of verification tools like Simulator, Synthesis etc.
• Hands on experience on C/C++, System Verilog, UVM, SystemC, RTL
• Understanding of some of the standard protocol interfaces like AMBA, Automotive, PCIe, USB etc.
• Excellent written and verbal interpersonal skills
• Self-motivated and great teammate
• Strong knowledge Design & Verification methodologies of either of these (Times/Untimed SW Models), RTL IP, VIPs, UVM Env.
• Understanding of verification tools like Simulator, Synthesis etc.Hands on experience on C/C++, System Verilog, UVM, SystemC, RTL
• Understanding of some of the standard protocol interfaces like AMBA, Automotive, PCIe, USB etc.
• Excellent written and verbal interpersonal skills
• Self-motivated and great teammate

Location

• Bangalore
• Bangalore

Location

• Bangalore
• Bangalore