ASIC Design Verification Engineer

Nsemi Design Services India Pvt Ltd; Bengaluru; On-site; INR 1,200,000 - 1,600,000; Full time

Job summary

Nsemi Design Services India Pvt Ltd is seeking an ASIC Design Verification Engineer to validate complex ASIC designs using UVM and SystemVerilog. You will develop test plans, create testbenches, and identify issues to ensure high performance and quality.

The role emphasizes hands-on verification within a collaborative team, focusing on reusable components and efficient verification methodologies. Bengaluru location, full-time position.

Qualifications

• Minimum 3+ years of experience with SystemVerilog and UVM.
• Bachelor's or Master’s Degree in Electronics/Electrical/Telecom/VLSI Engineering required.
• Hands-on experience with RTL and SystemVerilog-based verification is preferred.

Responsibilities

• Break RTL modules using UVM and develop reusable verification components and testbenches.
• Develop comprehensive test plans and testbenches to achieve code coverage targets.
• Collaborate with design teams and participate in design and code reviews.
• Test and verify complex ASIC designs to ensure performance and quality.

Skills

SystemVerilog

UVM

C/C++

SystemC

RTL

Verification-methodologies

Education

Bachelor's or Master's in Electronics or Electrical or Telecom or VLSI Engineering

Tools

Simulator

Synthesis

Job description

As an ASIC Design Verification Engineer at Nsemi, you will play a crucial role in ensuring the functionality and reliability of our cutting-edge ASIC designs. You will utilize advanced verification methodologies, including UVM and SystemVerilog, to develop comprehensive test plans, create and execute testbenches, and identify and resolve potential issues. Your work will be pivotal in validating complex designs and ensuring they meet the highest standards of performance and quality. If you have a passion for functional verification and a keen eye for detail, this role offers an exciting opportunity to contribute to groundbreaking semiconductor projects.

ASIC Design Verification Engineer

As an ASIC Design Verification Engineer at Nsemi, you will play a crucial role in ensuring the functionality and reliability of our cutting-edge ASIC designs. You will utilize advanced verification methodologies, including UVM and SystemVerilog, to develop comprehensive test plans, create and execute testbenches, and identify and resolve potential issues. Your work will be pivotal in validating complex designs and ensuring they meet the highest standards of performance and quality. If you have a passion for functional verification and a keen eye for detail, this role offers an exciting opportunity to contribute to groundbreaking semiconductor projects.

ASIC Design Verification Engineer

As an ASIC Design Verification Engineer at Nsemi, you will play a crucial role in ensuring the functionality and reliability of our cutting-edge ASIC designs. You will utilize advanced verification methodologies, including UVM and SystemVerilog, to develop comprehensive test plans, create and execute testbenches, and identify and resolve potential issues. Your work will be pivotal in validating complex designs and ensuring they meet the highest standards of performance and quality. If you have a passion for functional verification and a keen eye for detail, this role offers an exciting opportunity to contribute to groundbreaking semiconductor projects.

Qualification Required

• Typically requires minimum of 3+ years of experience in System Verilog, UVM.


• Bachelors OR Master’s Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering.


• Typically requires minimum of 3+ years of experience in System Verilog, UVM.


• Bachelors OR Master’s Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering.

Roles And Responsibilities

• As a member of the design verification team, it is your job to break things. You will work with logic designers to test RTL modules using UVM and will have the opportunity to develop re-usable verification components and testbenches.


• If you thrive in a collaborative environment (even while social distancing) and enjoy learning new techniques and approaches for verification and tooling while working on machine learning acceleration hardware for Azure, then this is the position for you. Responsible for the on-time delivery of block-level layouts, with acceptable quality.


• You will develop testbench components and stimulus using System Verilog UVM libraries. On a small, agile team, you will start from microarchitectural specifications and develop test environments and test plans to achieve code coverage targets. You will collaborate via design reviews and code reviews.


• As a member of the design verification team, it is your job to break things. You will work with logic designers to test RTL modules using UVM and will have the opportunity to develop re-usable verification components and testbenches.


• If you thrive in a collaborative environment (even while social distancing) and enjoy learning new techniques and approaches for verification and tooling while working on machine learning acceleration hardware for Azure, then this is the position for you. Responsible for the on-time delivery of block-level layouts, with acceptable quality.


• You will develop testbench components and stimulus using System Verilog UVM libraries. On a small, agile team, you will start from microarchitectural specifications and develop test environments and test plans to achieve code coverage targets. You will collaborate via design reviews and code reviews.

Required Technical And Professional Expertise

• Strong knowledge Design & Verification methodologies of either of these (Times/Untimed SW Models), RTL IP, VIPs, UVM Env.


• Understanding of verification tools like Simulator, Synthesis etc.


• Hands on experience on C/C++, System Verilog, UVM, SystemC, RTL


• Understanding of some of the standard protocol interfaces like AMBA, Automotive, PCIe, USB etc.


• Excellent written and verbal interpersonal skills


• Self-motivated and great teammate


• Strong knowledge Design & Verification methodologies of either of these (Times/Untimed SW Models), RTL IP, VIPs, UVM Env.


• Understanding of verification tools like Simulator, Synthesis etc.


• Hands on experience on C/C++, System Verilog, UVM, SystemC, RTL


• Understanding of some of the standard protocol interfaces like AMBA, Automotive, PCIe, USB etc.


• Excellent written and verbal interpersonal skills


• Self-motivated and great teammate

Location

• Bangalore


• Bangalore