Lead RTL Design Engineer

Cadence System Design and Analysis; New Delhi; On-site; Full time

Job description

Looking for Senior Leadership Team in Design Verification, DFT, PD, I have something very exciting Opportunity those are ready to lead the Larger...

• Proficient in Verilog coding and RTL design, data path designs
• Knowledge of RTL checks ex- LINT, SDC, CDC
• Familiar with synthesis flow and timing constraints
• Experience in writing Verilog testbench and running simulations.
• Familiar with any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display

Seniority level

• Mid-Senior level

Employment type

• Full-time

Job function

• Semiconductor Manufacturing

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