Principal IP/RTL Design Engineer for TPU / GPU

Mulya Technologies; Bengaluru; On-site; INR 2,500,000 - 3,500,000; Full time

Benefits offered by this job

Meritocracy-first workplace

Competitive salary

Opportunity to learn from industry veterans

Job summary

A semiconductor design company in Bengaluru is seeking a Mid-Senior level IP/RTL Design Engineer with extensive experience in designing IP for high-performance computing. The role includes designing TPU cores and involves a strong knowledge of GPU/TPU architectures. Candidates should have a BS/MS in Electrical/Computer Engineering and at least 10 years of relevant experience. This role offers a chance to work on cutting-edge technology in a startup environment.

Qualifications

• 10+ years in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or GPU/TPU architectures.
• Experience with AXI, NoC, or similar interconnect protocols.
• Familiarity with LPDDR6, HBM3, DDR5 memory interfaces.

Responsibilities

• Design IP blocks for TPU cores, including systolic arrays and memory subsystems.
• Develop RTL for performance, timing, and area optimization.
• Implement high-speed interconnects for TPU/GPU data pipelines.

Skills

Verilog/SystemVerilog RTL design

Problem-solving

Teamwork

Education

BS/MS in Electrical/Computer Engineering

Tools

Synopsys Design Compiler

Job description

Position Overview

Seeking an IP/RTL Design Engineer with 5+ years of experience to design IP/RTL for TPUs, focusing on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration.

Key Responsibilities

• Design IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems.
• Develop Verilog/SystemVerilog RTL for performance, timing, and area optimization.
• Implement high-speed interconnects (e.g., AXI, NoC) for TPU / GPU data pipelines.
• Optimize designs for high throughput, low latency, and power efficiency in AI workloads.
• Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces.
• Support synthesis, timing closure, and FPGA prototyping and Design Verification teams.
• Document microarchitecture and design specifications.

Required Qualifications

• Education: BS/MS in Electrical/Computer Engineering.
• Experience: 10+ years in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or GPU / TPU-like architectures.
• Skills: Proficient in Verilog/SystemVerilog RTL design.
• Knowledge: GPU/TPU architectures, systolic arrays, or matrix multiplication units.
• Experience with AXI, NoC, or similar interconnect protocols.
• Familiarity with LPDDR6, HBM3, DDR5, or high-bandwidth memory interfaces.
• Proficiency with synthesis and timing tools (e.g., Synopsys Design Compiler).
• Strong problem-solving and teamwork skills.

Preferred Qualifications

• Experience with AI/ML workloads or datacenter TPU designs and GPU architectures
• Knowledge of CXL, PCIe, UALink, or Ultra Ethernet.
• Familiarity with power optimization for high-performance chips.

What is in it for you?

• Pure play product work environment
• Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world
• Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market.
• A meritocracy-first workplace where each peer is a star
• A chance to be part of an industry-shaping product in its entirety (not bits and pieces) from initial stages
• A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them).
• A chance to learn from industry veterans who have launched multiple Billion Dollar Semiconductor firms over the last 3 decades.

Contact

Mining The Knowledge Community

Seniority level

• Mid-Senior level

Employment type

• Full-time

Job function

• Design, Research, and Engineering

Industries

• Semiconductor Manufacturing
• Computer Hardware Manufacturing
• Telecommunications