Mixed-Signal Design RTL Design Engineer

TylSemi, Inc.; Karnataka; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

TylSemi, Inc. is seeking a professional in Bengaluru to architect and implement digital PID control loops for high-frequency power delivery systems. Candidates should have a solid background in mixed-signal design and expert MATLAB/Simulink experience. The role involves model development, collaboration with analog designers, and direct contributions to cutting-edge silicon solutions.

An offer of a hybrid work environment is available, emphasizing a fast-paced team adaptable to groundbreaking technological shifts in the semiconductor industry.

Qualifications

• Solid understanding of analog power circuits and digital control systems.
• Experience converting MATLAB/Simulink algorithms into RTL.
• Familiarity with mixed-signal verification.

Responsibilities

• Architect and implement digital control loops for high-frequency IVRs.
• Develop high-fidelity plant models using MATLAB/Simulink.
• Collaborate with analog designers on control and sensor design.

Skills

Mixed-signal background

Expert-level MATLAB/Simulink

RTL conversion

Digital PID implementation challenges

High-frequency power converter control

Mixed-signal verification flows

Digital design tools proficiency

Education

BSEE/MSEE or PhD with 8+ years relevant experience

Tools

Synopsys VCS

Design Compiler

Job description

Overview

The AI infrastructure market is exploding. Every hyperscaler, cloud provider, and AI company is building custom silicon, and they all confront the same challenge: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package? TYLsemi solves this by building chiplet infrastructure IP – the IO, power delivery, and interconnect building blocks that make AI/HPC systems work at scale. This is not a nice‑to‑have; it is the critical path.

Market Opportunity

The semiconductor industry is undergoing its biggest architectural shift in 40 years. Moore’s Law is fading; custom silicon is mainstream; and IO and power are the bottlenecks. We are entering the market at the exact moment every major AI/HPC player needs what we build, and their alternatives are disappearing.

Culture & Team

• We have no politics, no bureaucracy, and no approval chains.
• Ideas are tested and shipped if they work – no endless meetings or PowerPoint presentations.
• Remote‑friendly, global team: US team prefers the Bay Area but hires the best regardless of location; India team is building a world‑class design center in Bangalore.
• Fast pace: We ship real products, have paying customers, committed capital, and aggressive timelines.
• Ownership mindset: Define and execute your own roadmap.
• Bias for action: Move fast; analysis paralysis is not accepted.
• Deep technical expertise: Ship real silicon and debug real hardware.
• Low ego, high standards: Results matter more than titles or politics.

Responsibilities

• Architect, model, and implement digital PID / cascade control loops (voltage‑mode, current‑mode, or hybrid) for high‑frequency multi‑phase IVRs operating at 10–100MHz.
• Develop high‑fidelity plant models in MATLAB / Simulink (averaged and switched) using extracted parasitics from Ansys Q3D / SIwave.
• Perform closed‑loop stability analysis on switched power stages.
• Translate validated MATLAB/Simulink controller models into production‑quality RTL (Verilog / SystemVerilog) using HDL Coder or manual coding.
• Design and implement supporting digital blocks such as ADC interface and DPWM (digital PWM).
• Collaborate closely with analog designers on loop compensation, sensor design, quantization effects, and delay budgeting.
• Perform mixed‑signal verification: co‑simulation of RTL (VCS / Xcelium) with analog models (Spectre / APS) and behavioral models (Simulink / SIMPLIS / PLECS).
• Analyze and optimize for area, power, timing, and metastability across PVT corners in the digital controller.
• Support silicon bring‑up, debug, and controller tuning on lab hardware.

Qualifications

• Strong mixed‑signal background: solid understanding of analog power circuits (buck converters, 3‑level buck, hybrid SC‑inductor topologies) and digital control systems.
• Expert‑level MATLAB / Simulink experience: building averaged and switched power converter models, using Control System Toolbox, Simscape Electrical, frequency‑response estimation, PID tuning, and discrete‑time controller design.
• Proven experience converting MATLAB/Simulink control algorithms into clean, synthesizable RTL (HDL Coder or hand‑coded Verilog/SystemVerilog).
• Deep knowledge of digital PID implementation challenges: quantization, sampling effects, computational delay, fixed‑point arithmetic, limit cycling.
• Familiarity with high‑frequency power converter control (10–100 MHz) and digital PWM modulators (DPWM).
• Experience with mixed‑signal verification flows (analog‑digital co‑simulation).
• Good understanding of analog effects impacting digital control: loop delay, sensor non‑idealities, inductor non‑linearities, PDN resonances.
• Proficiency with digital design tools: Synopsys VCS, Verdi, Design Compiler, PrimeTime (or equivalent Cadence flow).
• BSEE/MSEE or PhD with 8+ years of relevant experience in power management ICs or high‑performance mixed‑signal design.

Good to Have

• Experience designing digital controllers for integrated voltage regulators (IVRs), point‑of‑load converters, or high‑current AI/HPC power delivery.
• Knowledge of advanced topologies: 3‑level buck, multi‑level converters, hybrid switched‑capacitor + inductive converters.
• Experience with package‑integrated magnetics, high‑permeability materials, and PDN modeling (Ansys Q3D / SIwave).
• Experience with formal verification or assertion‑based mixed‑signal verification.

Location

Hybrid / On‑site – Bengaluru

Equal Opportunity

We are an equal‑opportunity employer committed to diversity and inclusion. All qualified applicants will receive consideration for employment.