Senior Staff Engineer - Physical Design

Jobgether; India; Hybrid; INR 4,500,000 - 7,500,000; Full time

Benefits offered by this job

Remote-friendly in India

Ownership and leadership role

Mentoring and growth

AI/ML design focus

Job summary

Jobgether seeks a Senior Staff Engineer - Physical Design for a partner in India. Lead end-to-end physical implementation for advanced semiconductor and AI/HPC designs, from floorplanning through tape-out with a strong emphasis on PPA and reliability.

You will collaborate with RTL, STA, DFT, package, and CAD teams, shape design methodologies, and drive automation while delivering high-quality silicon on time.

Qualifications

• 12+ years of hands-on ASIC/SoC physical design implementation experience.
• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or related field.
• Proficiency with Cadence Innovus, Synopsys ICC2, PrimeTime, StarRC; strong floorplanning and timing knowledge.

Responsibilities

• Lead full-chip or block-level physical design from floorplanning to GDS signoff.
• Optimize timing, power, area and reliability across advanced nodes.
• Collaborate with RTL, DFT, STA, package, and CAD teams to resolve signoff issues.
• Develop and improve physical design flows, automation and methodologies.
• Mentor junior engineers and contribute to a strong design culture.
• Support tape-out planning and milestone delivery.

Skills

Leadership

Cross-functional collaboration

Mentoring

Problem-solving

Ownership mindset

Education

Bachelor’s or Master’s degree in Electronics/Electrical/VLSI

Tools

Cadence Innovus

Synopsys ICC2

PrimeTime

StarRC

Tcl

Python

Perl

Job description

Senior Staff Engineer - Physical Design

This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Senior Staff Engineer - Physical Design based in India.

This is a senior technical leadership opportunity focused on end-to-end physical implementation for advanced semiconductor and AI/HPC designs.

You will lead complex block- and full-chip implementation activities from floorplanning through physical signoff and tape-out.

The role has a strong emphasis on achieving demanding power, performance, area, timing, and reliability targets.

You will collaborate closely with RTL, STA, DFT, package, and CAD teams to solve challenging implementation and signoff issues.

The position also offers the opportunity to shape physical design methodologies, automation, and engineering best practices.

You’ll work in a fast-moving, low-bureaucracy environment where deep technical expertise, ownership, and execution are highly valued.

Based in Bengaluru with a remote-friendly setup, this role is suited to an experienced engineer who wants to make a direct impact on next-generation AI infrastructure.

Accountabilities

• Lead physical design implementation: Own full-chip or block-level physical implementation from floorplanning and power planning through placement, CTS, routing, optimization, physical verification, and GDS signoff.
• Drive PPA and reliability optimization: Analyse and optimise timing, congestion, power, IR drop, electromigration, and signal integrity across advanced technology nodes.
• Manage signoff closure: Identify and resolve implementation issues and ensure high-quality closure across timing, power, area, and reliability requirements.
• Collaborate cross-functionally: Partner with RTL, DFT, STA, package, and CAD teams to address complex implementation, integration, and signoff challenges.
• Improve physical design methodologies: Develop and enhance implementation flows, automation scripts, tools, and methodologies to improve engineering efficiency and design quality.
• Support tape-out: Contribute to tape-out planning and execution while ensuring implementation milestones and signoff deliverables are completed with minimal schedule impact.
• Provide technical leadership: Participate in technical reviews, establish best practices, and proactively identify implementation bottlenecks and risks.
• Mentor engineers: Guide junior team members, share technical expertise, and contribute to the development of a strong physical design engineering culture.
• Drive innovation: Explore emerging approaches, including AI/ML-assisted design optimisation, to improve physical implementation workflows and outcomes.

Requirements

• Experience: 12+ years of hands‑on experience in ASIC/SoC physical design implementation.
• Education: Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or a related technical discipline.
• EDA expertise: Strong proficiency with industry‑standard physical design and signoff tools such as Cadence Innovus, Synopsys ICC2, PrimeTime, and StarRC.
• Physical design: Deep understanding of floorplanning, power planning, placement, clock‑tree synthesis, routing, optimisation, physical verification, and signoff.
• Timing & reliability: Strong knowledge of timing closure, low‑power design techniques, signal integrity, IR/EM analysis, and physical verification.
• Advanced nodes: Experience working on advanced semiconductor technology nodes, with 7nm, 5nm, or 3nm experience preferred.
• Automation: Strong scripting capabilities in Tcl, Perl, and/or Python for flow development, automation, and methodology improvements.
• SoC integration: Experience with hierarchical and top‑level SoC integration is desirable.
• Emerging technologies: Exposure to ML/AI‑based physical design optimisation is a plus.
• Advanced packaging: Knowledge of package‑aware implementation and multi‑die or chiplet architectures is advantageous.
• Problem‑solving: Excellent debugging, analytical, and problem‑solving skills, with the ability to tackle complex implementation challenges independently.
• Leadership & collaboration: Strong communication and stakeholder‑management skills, combined with the ability to influence technical decisions and work effectively across engineering disciplines.
• Mindset: A strong ownership mentality, bias for action, low‑ego approach, and commitment to high technical standards.

Benefits

• Remote‑friendly working environment in India.
• Opportunity to work on next‑generation semiconductor infrastructure for AI and high‑performance computing.
• High‑impact technical role with significant ownership over physical design methodologies and implementation.
• Fast‑paced engineering environment with minimal bureaucracy and a strong focus on execution.
• Opportunity to collaborate with experienced semiconductor professionals on complex, production‑focused designs.
• Exposure to advanced technology nodes, chiplet architectures, and emerging AI/ML‑driven design methodologies.
• Significant opportunities for technical leadership, mentoring, and professional growth.
• Opportunity to contribute directly to products addressing critical challenges in AI infrastructure.