CPU/ GPU Verification-Technical Manager

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru seeks an experienced CPU/GPU/SoC/IP Lead Engineer to lead architecture, design, integration and execution of complex semiconductor products, from specification through tape-out. The role requires deep hands-on Verilog/SystemVerilog RTL skills, IP integration, and experience with AMBA/AXI/NoC interfaces, high-speed protocols, and ASIC design flows.

You will mentor engineers and coordinate with Architecture, Design, Verification, Physical Design and

Qualifications

• Experience in CPU/GPU/SoC/IP design and architecture.
• Strong RTL design and Verilog/SystemVerilog expertise.
• IP integration and ASIC design flows experience.
• Knowledge of AMBA/AXI/NoC interfaces and high-speed protocols.
• Leadership of technical teams and project execution.

Responsibilities

• Lead architecture, micro-architecture, RTL design and integration of CPU/GPU/SoC/IP blocks.
• Drive execution from specification through verification, sign-off and tape-out.
• Own IP integration and top-level SoC design including clock/reset and interconnect.
• Collaborate with Architecture, Design, Verification, Physical Design, DFT, Firmware and Post-Silicon teams.
• Drive PPA optimization and design quality.
• Review design/verification plans and resolve RTL, integration and system issues.
• Mentor senior/junior engineers and provide technical direction.
• Support pre-silicon and post-silicon debug including emulation and silicon bring-up.

Skills

CPU/GPU/SoC design

RTL design

Verilog/SystemVerilog

IP integration

ASIC design flow

AMBA/AXI/NoC

PPA optimization

Tape-out experience

Technical leadership

Education

B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, Computer Engineering, VLSI

Tools

Emulation

FPGA prototyping

Job description

We are looking for an experienced CPU/GPU/SoC/IP Lead Engineer to lead the architecture, design, integration, and execution of complex semiconductor products. The candidate should have strong expertise in CPU/GPU architecture, SoC/IP development, RTL design, IP integration, and ASIC development, with proven experience taking projects from specification through tape-out.

Key Responsibilities

• Lead architecture, micro-architecture, RTL design and integration of complex CPU/GPU/SoC/IP blocks.
• Drive technical execution from specification, architecture and RTL through verification, sign-off and tape-out.
• Own IP integration and top-level SoC design, including interfaces, clock/reset, power and interconnect architecture.
• Work closely with Architecture, Design, Verification, Physical Design, DFT, Firmware and Post-Silicon teams.
• Drive PPA (Power, Performance & Area) optimization and design quality.
• Review design/verification plans and resolve complex RTL, integration and system-level issues.
• Drive technical discussions, identify risks and ensure timely project execution.
• Mentor senior/junior engineers and provide technical direction to the team.
• Support pre-silicon and post-silicon debug, including emulation and silicon bring-up where required.

Must-Have Skills

• Strong experience in CPU / GPU / SoC / IP design.
• Excellent understanding of Digital ASIC design and SoC architecture.
• Strong hands-on experience with Verilog/SystemVerilog and RTL design.
• Experience with IP integration, SoC-level integration and ASIC design flows.
• Good understanding of AMBA/AXI/CHI, NoC, memory subsystem and high-speed interfaces.
• Experience with Lint, CDC/RDC, synthesis, STA and RTL quality checks.Strong understanding of clock/reset, power management and low-power design concepts.
• Proven experience in leading technical teams and driving projects to successful delivery.
• Strong problem-solving, communication and stakeholder-management skills.

Preferred

• Experience with ARM/x86/RISC-V CPU architecture or GPU architecture.
• Experience with PCIe, DDR, UCIe, CXL or other high-speed protocols.
• Exposure to emulation, FPGA prototyping and silicon debug.
• Multiple successful tape-out / first-silicon experience.
• Experience working with global engineering teams and IP vendors.

Education

B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, Computer Engineering, VLSI or a related discipline.

Immediate joiners / candidates with 0–30 days notice will be highly preferred.