Principal Engineer – Design Verification

Upscale AI; Bengaluru; On-site; INR 3,500,000 - 7,000,000; Full time

Job summary

Upscale AI in Bengaluru seeks a senior ASIC/SoC verification expert to lead the verification of high‑performance networking IPs and large subsystems.

You will architect scalable UVM environments, author rigorous test plans, drive regressions, and mentor a team while collaborating with Design and Architecture to ensure high‑quality delivery.

Qualifications

• 15+ years of ASIC/SoC design verification experience.
• Experience in the networking domain and verifications of high‑throughput designs.
• Mastery of SystemVerilog and UVM, with complex testbenches and VIP integrations.
• Experience leading verification at IP and Sub‑system levels and SoC integration.
• BTech/MTech in Electronics/Electrical Engineering, Computer Engineering, or related field.

Responsibilities

• Own the complete verification lifecycle for high‑performance networking IPs and large‑scale sub-systems.
• Architect, develop, and maintain advanced constrained‑random UVM environments from scratch.
• Author verification plans and drive regression, triage, and coverage closure.
• Debug deeply with expert-level debugging for complex hardware bugs.
• Lead through code reviews and ensure reuse and documentation quality.
• Collaborate with Design and Architecture to resolve ambiguities early in the design cycle.

Skills

System Verilog

UVM

ASIC Verification

SoC integration

IP verification

Testbenches

VIP integration

Leadership

Python

Perl

Education

BTech/MTech in Electronics/EE or CE

Tools

FPV

Job description

Key Responsibilities

• IP & Sub-system Leadership: Own the complete verification lifecycle for critical high-performance networking IPs and large-scale sub-systems.
• UVM Environment Architecture: Architect, develop, and maintain advanced, scalable constrained-random verification environments from scratch using System Verilog and UVM.
• Test Planning & Execution: Author comprehensive, bulletproof verification plans. Drive test case development, regressions, triage, and coverage closure (functional, code, and assertion-based metrics).
• Advanced Debugging: Serve as the team's go-to expert for isolating and resolving the most complex, deep‑seated hardware bugs.
• Lead by Example: Actively participate in design and verification code reviews. Maintain high standards of code quality, reuse, and documentation within the execution team.
• Cross‑Functional Alignment: Partner closely with Design and Architecture teams to resolve ambiguities early in the design cycle and ensure high-quality delivery.

Required Qualifications & Skills

• 15+ years of solid experience in ASIC/SoC Design Verification with a proven track record of successful tape‑outs.
• Extensive experience in the networking domain, verifying high‑throughput, data‑intensive designs.
• Mastery of System Verilog and UVM. Proven history of writing complex testbenches and VIP integrations from scratch.
• Experience leading verification at the IP and Sub‑system level, with strong exposure to SoC integration.
• B Tech/M Tech in Electronics/Electrical Engineering, Computer Engineering, or a related field.

Preferred / Added Advantages

• Hands‑on experience with Formal Property Verification (FPV) to exhaustively verify block‑level control logic.
• Proficiency in Python or Perl for testbench automation and triage scripting.

Equal Opportunity

Upscale AI is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

Accessibility & Accommodations

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