Senior Principal Engineer - Design Verification

Upscale AI; Bengaluru; On-site; INR 10,000,000 - 15,000,000; Full time

Job summary

Upscale AI in Bengaluru, India, is seeking a Senior Principal DV Engineer to define the global verification strategy for massive-scale networking SoCs. This elite technical leadership role requires driving the verification methodology, guiding cross‑functional alignment from architecture to post‑silicon, and pioneering FPV and emulation techniques.

You will influence design architectures for verifiability, mentor Principal engineers, and engage with executive leadership to ensure zero‑defect

Qualifications

• 15+ to 17+ years of ASIC/SoC verification experience with large-scale tape-outs.
• Deep knowledge of networking domain and full‑chip verification constraints.
• Expertise in SystemVerilog, UVM, and verification planning.

Responsibilities

• Define and govern verification roadmap and methodology for multi‑million‑gate networking SoCs.
• Drive FPV adoption, emulation, and shift‑left verification within the SoC timeline.
• Set quality metrics, sign‑offs, and risk mitigation across project life cycle.
• Collaborate with Silicon Architects and Design Directors to optimize testability.
• Mentor senior engineers and foster engineering excellence across the site.

Skills

SoC Verification

SystemVerilog

UVM

FPV (Formal)

Executive communication

Education

B Tech/M Tech in Electronics/Electrical Engineering, Computer Engineering

Tools

Hardware Emulation (Palladium)

Zebu

Simulation frameworks

Job description

Why join Upscale AI

Upscale AI is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high‑performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real‑world impact.

If you’re looking to do high‑impact work, move fast, and help define the infrastructure behind the future of AI—Upscale AI is where you can produce meaningful work at the frontier—and operate at a high standard.

Experience Level: 17+ Years (or 15+ with exceptional strategic track record)

Location: Bangalore, India (On‑Site)

Position Type: Full‑Time

About the Role

We are seeking a visionary Senior Principal DV Engineer to define the global verification strategy for our massive‑scale networking SoCs. This is a high‑impact, elite technical leadership role. You will be responsible for defining the overarching SoC verification methodology, driving cross‑functional alignment from architecture to post‑silicon, and pioneering next‑generation verification technologies (such as Formal and Emulation). You will influence design architectures for verifiability and serve as a strategic technical advisor to executive leadership while steering the broader engineering organization.

Key Responsibilities

• SoC Verification Strategy: Define, architect, and govern the overarching verification roadmap and methodology for full‑scale, multi‑million gate networking SoCs.
• Methodology Innovation: Drive the adoption of advanced methodologies. Seamlessly integrate Formal Property Verification (FPV), hardware emulation, and advanced shift‑left strategies into the standard SoC timeline.
• High‑Level Governance: Establish, track, and enforce rigorous quality metrics and sign‑off criteria across the entire project lifecycle, ensuring zero‑defect silicon.
• Architectural Influence: Work directly with Silicon Architects and Design Directors to review specs, optimize micro‑architecture for testability/verifiability (DFV), and mitigate risk early.
• Organizational Mentorship: Mentor Principal engineers and technical leads across the site. Champion best practices, drive technical brainstorming, and cultivate a culture of engineering excellence.
• Crisis Debugging & Escalation: Act as the ultimate technical authority for critical, complex issues that block project milestones or require deep cross‑functional triage.

Required Qualifications & Skills

• Experience: 15+ to 17+ years of distinguished experience in ASIC/SoC Verification, having successfully guided multiple complex, large‑scale tape‑outs from concept to production.
• Domain Leadership: Deep, comprehensive knowledge of the networking domain, with an understanding of how system‑level traffic flow impacts full‑chip verification constraints.
• Full‑Scale SoC Scope: Proven experience leading full SoC‑level verification environments, managing top‑level testbenches, and coordinating multi‑subsystem integration.
• Expertise: Authoritative knowledge of System Verilog, UVM, and structural verification planning.
• Influence & Communication: Outstanding executive communication skills. Ability to articulate complex technical risks and trade‑offs clearly to both engineering teams and executive management.
• Education: B Tech/M Tech in Electronics/Electrical Engineering, Computer Engineering, or a related field.

Preferred / Added Advantages

• Strong, proven track record of deploying Formal Verification (FPV) at scale to displace traditional simulation.
• Experience integrating hardware emulation (e.g., Palladium, Zebu) into a unified simulation workflow.

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

Equal Opportunity

Upscale AI is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

Accessibility & Accommodations

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at [e-mail]—we’re happy to help. Note: This inbox is only for accommodation requests.