Senior / Lead Verification Engineer

Zyoin Group; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

Zyoin Group is seeking a Senior/Lead Verification Engineer to own the functional verification of a high-performance signal processing ASIC. You will collaborate with RTL designers and architects to ensure design correctness before silicon, shaping verification strategy and mentoring teammates.

You will develop UVM-based testbenches for the on-chip network, PCIe endpoint, and inter-core synchronization, write SVA checks, and drive coverage and regression efforts across complex subsystems.

Qualifications

• 5–10 years RTL verification in ASIC/SoC environments.
• Strong SystemVerilog and UVM with testbench architecture and coverage.
• SVA assertions written from architecture specs.
• Proficient with AXI4/AHB/APB; PCIe TLP handling is a plus.
• Hands-on with simulators VCS/Xcelium/Questa and debugging tools.

Responsibilities

• Verify RTL blocks across multi-core vector processor subsystems.
• Develop UVM-based testbenches for on-chip network, PCIe, DMA, and inter-core sync.
• Write directed and constrained-random test cases for custom ISA opcodes.
• Create SVA assertions for AXI4-Lite and flow-control logic.
• Verify clock domain crossings and protocol timing across subsystems.
• Validate RISC-V system management boot flow and reset sequencing.
• Drive functional and code coverage closure; debug RTL failures end-to-end.
• Build regression suites for multi-core coordination and events distribution.
• Verify PCIe endpoint and NoC; manage TLP handling and virtual channels.
• Automate test generation and regression analysis using Python/TCL.

Skills

RTL verification

SystemVerilog

UVM

SVA assertions

AXI4/AHB/APB

PCIe TLP

VCS/Xcelium/Questa

Verdi/SimVision

Python/TCL scripting

SoC/NoC verification

independent work

Tools

VCS

Xcelium

Questa

Verdi

SimVision

Job description

Our Client is a signal processing infrastructure company. they build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical workloads.

Our Client’s Silicon is their ground-up effort to build a new compute category.

About the Role

We are building a high-performance signal processing ASIC a multi-core vector processor with a custom ISA, targeting defense, 5G, and test & measurement markets. As a Senior/Lead Verification Engineer, you will own functional verification for major subsystems of the chip, from testbench architecture through coverage closure. You will work closely with RTL designers and the architecture team to build the verification environments, assertions, and test plans that prove the design matches spec before it goes to silicon, and will help set verification methodology and mentor other engineers on the team.

Responsibilities

• Verify RTL blocks across client's custom multi-core vector processor — execution units, register files, datapath pipelines, and arithmetic units (integer, fixed-point, floating-point, complex)
• Develop UVM-based SystemVerilog testbenches for the on-chip network, switch fabric, PCIe endpoint, DMA engines, and inter-core synchronization engine
• Write directed and constrained-random test cases targeting custom ISA opcodes, data types, and pipeline hazard scenarios
• Write SVA assertions for protocol compliance across AXI4-Lite bus fabric, credit-based flow control, and virtual channel logic
• Verify clock domain crossings async FIFOs, gray-code pointers, 2FF synchronizers across all subsystem boundaries
• Verify the RISC-V system management controller — boot flow, reset sequencing, phased initialization, and mode switching
• Drive functional and code coverage closure across all execution unit opcodes and supported data types
• Debug RTL failures across the full design hierarchy — waveform tracing, root-cause analysis, and tracking to resolution with RTL engineers
• Build and maintain regression suites for multi-core coordination, barrier logic, and event distribution scenarios
• Verify PCIe endpoint and NoC (network-on-chip) — TLP handling, credit flow control, virtual channels
• Verify microprocessor/RISC-V core-level functionality — instruction execution, pipeline behavior, and processor compliance
• Automate test generation and regression analysis using Python or TCL scripting

Requirements

Experience

• 5 to 10 years of RTL verification experience in ASIC or SoC environment
• Strong SystemVerilog and UVM — testbench architecture, sequences, scoreboards, monitors, functional and code coverage
• SVA assertion writing from architecture specifications — not just consuming existing assertions
• Protocol knowledge — AXI4, AHB, APB; PCIe TLP handling a strong plus
• Hands-on with simulation tools — VCS, Xcelium, or Questa
• Strong debugging skills — comfortable tracing failures across deep design hierarchy in Verdi or SimVision
• Understanding of processor pipelines — hazard detection, data forwarding, multi-cycle operations
• Python or TCL scripting for regression automation and test generation
• Ability to work independently from a detailed architecture specification
• SoC, NoC, PCIe, and microprocessor-level verification experience

Good to have

• Formal verification — JasperGold, VC Formal, or Questa Formal for exhaustive property checking on arithmetic units and control logic