Principal Engineer – Design Verification

The Consensus; Bengaluru; On-site; INR 4,000,000 - 10,000,000; Full time

Job summary

Upscale AI in Bengaluru seeks a highly technical Principal DV Engineer to anchor verification of next-gen high-performance networking silicon. Lead verification lifecycle for IPs and subsystems, architect UVM environments, write tests, drive coverage, and mentor the team.

Requires 15+ years in ASIC/SoC DV, mastery of SystemVerilog and UVM, and track record in IP/subsystem verification and VIP integration. Experience with FPV and Python/Perl scripting is a plus. Equal opportunity employer.

Qualifications

• 15+ years of ASIC/SoC DV with a track record of successful tape-outs.
• Expert in SystemVerilog and UVM; proven history of writing complex testbenches and VIP integrations from scratch.
• Leading verification at IP and Sub-system level with exposure to SoC integration.
• Bachelor/Master in Electronics/Electrical Engineering or Computer Engineering or related field.

Responsibilities

• Own the verification lifecycle for critical networking IPs and large-scale sub-systems.
• Architect, develop, and maintain advanced constrained-random UVM environments.
• Drive test planning, regressions, triage, and coverage closure (functional, code, and assertion-based).
• Debug complex hardware bugs and mentor the verification team.
• Lead by example in design and verification reviews; ensure quality and reusable code.
• Collaborate with Design and Architecture to resolve ambiguities and ensure high-quality delivery.

Skills

SystemVerilog

UVM

IP/Subsystem verification

VIP integration

Mentoring

Education

B Tech/M Tech in Electronics/Electrical Engineering or Computer Engineering

Tools

Python

Perl

FPV

Job description

Why join Upscale AI

Upscale AI is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world's most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

If you're looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale AI is where you can produce meaningful work at the frontier—and operate at a high standard.

We are looking for a highly technical, hands-on Principal DV Engineer to anchor the verification of our next-generation, high-performance networking silicon. In this role, you will be the primary technical driver for complex IPs and critical sub-systems. You will balance advanced architectural environment creation with rigorous execution, leading by example on the engineering floor. This position is ideal for a veteran engineer who loves breaking complex designs, building elite UVM environments, and mentoring the next generation of verification talent.

Key Responsibilities

• IP & Sub-system Leadership: Own the complete verification lifecycle for critical high-performance networking IPs and large-scale sub-systems.
• UVM Environment Architecture: Architect, develop, and maintain advanced, scalable constrained-random verification environments from scratch using System Verilog and UVM.
• Test Planning & Execution: Author comprehensive, bulletproof verification plans. Drive test case development, regressions, triage, and coverage closure (functional, code, and assertion-based metrics).
• Advanced Debugging: Serve as the team's go-to expert for isolating and resolving the most complex, deep-seeded hardware bugs.
• Lead by Example: Actively participate in design and verification code reviews. Maintain high standards of code quality, reuse, and documentation within the execution team.
• Cross-Functional Alignment: Partner closely with Design and Architecture teams to resolve ambiguities early in the design cycle and ensure high-quality delivery.

Required Qualifications & Skills

• Experience: 15+ years of solid experience in ASIC/SoC Design Verification with a proven track record of successful tape-outs.
• Domain Expertise: Extensive experience in the networking domain, verifying high-throughput, data-intensive designs.
• Methodology Expert: Mastery of System Verilog and UVM. Must have a proven history of writing complex testbenches and VIP integrations from scratch.
• Verification Scope: Proven experience leading verification at the IP and Sub-system level, with strong exposure to SoC integration.
• Education: B Tech/M Tech in Electronics/Electrical Engineering, Computer Engineering, or a related field.

Preferred / Added Advantages

• Hands-on experience with Formal Property Verification (FPV) to exhaustively verify block-level control logic.
• Proficiency in Python or Perl for testbench automation and triage scripting.

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

Equal Opportunity

Upscale AI is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We're proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

Accessibility & Accommodations

We're committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at [e-mail]—we’re happy to help. Note: This inbox is only for accommodation requests.