Senior DFT Designer

NXP Semiconductors NV; Bengaluru; Presencial; INR 4 000 000 - 6 000 000; Tempo integral

Resumo da oferta

NXP Semiconductors NV in Bengaluru seeks an experienced Senior DFT Designer to contribute to cutting-edge mixed-signal and digital ICs. You will design, implement, and verify DFT architectures for complex SoCs, working closely with RTL, physical design, verification, product and test teams to ensure robust testability and high-quality silicon.

The role emphasizes leadership in DFT flows, memory BIST, ATPG, JTAG, and low-power DFT techniques, with mentorship of junior engineers and strong

Qualificações

• Bachelor or master in microelectronics, ECE or related field.
• Experience with DFT methodologies including Scan, MBIST, LBIST, JTAG.
• Hands-on ATPG tool experience for production tests.
• Knowledge of UPF/CPF low-power DFT techniques.
• Familiarity with physical design constraints for DFT.
• Experience in silicon debug and ATE bring-up.
• Proficient in Verilog, SystemVerilog and VHDL.

Responsabilidades

• Lead and execute the full DFT design flow from spec to verification.
• Develop scan insertion, test compression and ATPG patterns.
• Implement memory BIST strategies.
• Collaborate with RTL, physical design, verification and product teams.
• Coordinate with RTL and physical design teams for DFT insertion and timing closure.
• Develop and implement innovative DFT architectures and design methodologies to meet challenging performance, power, area and quality targets.
• Optimize test coverage, pattern count and test time.
• Perform comprehensive DFT verification at RTL and gate level.
• Work with ATE teams for test program development and silicon bring-up.
• Participate in post-silicon validation and debug activities, identifying and resolving issues to ensure product quality.
• Mentor junior engineers, provide technical guidance, and contribute to continuous improvement of DFT design processes and methodologies.
• Generate detailed design documentation, including specifications, test plans, and design reviews.
• Stay abreast of industry trends, emerging technologies, and best practices in digital IC design.

Conhecimentos

DFT methodologies

Scan, MBIST, LBIST

ATPG tooling

UPF/CPF DFT

Fault models knowledge

Physical design constraints

Silicon debug

ATE bring-up

Verilog/SystemVerilog/VHDL

Team player

Formação académica

Bachelor's or Master's in Microelectronics / ECE

Ferramentas

Verilog

SystemVerilog

VHDL

Descrição da oferta de emprego

Job Summary

Seeking an experienced Senior DFT Designer to contribute to the development of cutting-edge mixed-signal and digital integrated circuits. This role involves responsibility for designing, implementing, and verifying DFT architectures for complex SoCs working closely with RTL, physical design, verification, product and test teams to ensure robust testability and high-quality silicon.

Job Responsibilities

• Lead and execute the full DFT design flow, including specification definition, architectural design, RTL coding (Verilog/SystemVerilog), synthesis, static timing analysis (STA), verification.
• Develop and integrate scan insertion, test compression, and ATPG patterns.
• Implement memory BIST strategies.
• Collaborate closely with digital, analog, mixed-signal, product, test and software teams.
• Collaborate with RTL and physical design teams for DFT insertion and timing closure.
• Develop and implement innovative DFT architectures and design methodologies to meet challenging performance, power, area and quality targets.
• Optimize test coverage, pattern count and test time.
• Perform comprehensive DFT verification at RTL and gate level.
• Work with ATE teams for test program development and silicon bring-up.
• Participate in post-silicon validation and debug activities, identifying and resolving issues to ensure product quality.
• Mentor junior engineers, provide technical guidance, and contribute to continuous improvement of DFT design processes and methodologies.
• Generate detailed design documentation, including specifications, test plans, and design reviews.
• Stay abreast of industry trends, emerging technologies, and best practices in digital IC design.

Requirements

• Bachelor or master degree in microelectronics, ECE or related
• Strong expertise in DFT methodologies: Scan, MBIST, LBIST, JTAG.
• Hands-on experience with industry standard ATPG tools.
• Proficiency in UPF/CPF-based low-power DFT.
• Knowledge of fault models (stuck-at, transition, path delay).
• Familiarity with physical design constraints for DFT.
• Experience in silicon debug and ATE bring-up
• Knowledge of Verilog, SystemVerilog, VHDL
• Strong commitment to schedule and quality, a good team player

More information about NXP in India…

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