Physical Design Practice head

ACL Digital; Bengaluru; On-site; INR 4,500,000 - 9,000,000; Full time

Job summary

ACL Digital Bangalore is seeking a Practice Head - Physical Design to lead, scale, and manage the VLSI Physical Design practice. You will drive the practice growth, oversee complex netlist-to-GDSII execution on advanced nodes, and lead a high-performing Bangalore team.

The role requires 15+ years in VLSI Physical Design with leadership experience and a proven tape-out track record on sub-7nm FinFET/GAA nodes.

Qualifications

• B.E./B.Tech/M.Tech in Microelectronics, VLSI, or Electronics Engineering.
• 15+ years in VLSI Physical Design with 5+ years leading practice/business units.
• Proven tape-out track record on sub-7nm FinFET/GAA nodes.
• Expertise in Synopsys (Fusion Compiler, PrimeTime) or Cadence (Innovus, Tempus) EDA suites.

Responsibilities

• Define the practice roadmap, drive revenue growth, manage utilization, and oversee business unit P&L.
• Partner with sales to lead RFPs, technical proposals, and client technical governance for global semiconductor accounts.
• Delivery Excellence: Provide technical leadership across Synthesis, Floorplanning, CTS, Routing, STA, and PV (DRC/LVS/EMIR) for complex SoCs/ASICs.
• Team Leadership: Build, mentor, and scale a world-class engineering team in Bangalore.

Skills

VLSI Physical Design

Leadership

Client Engagement

Strategy & Planning

Education

B.E./B.Tech/M.Tech in Microelectronics

Tools

Synopsys Fusion Compiler

PrimeTime

Cadence Innovus

Cadence Tempus

Job description

< p >Role: Practice Head - Physical Design (VLSI)

Experience: 15+ Years

Overview

We are looking for a Physical Design Practice Head to lead, scale, and manage our VLSI Physical Design business unit in Bangalore. You will drive practice growth, oversee complex netlist-to-GDSII execution on advanced nodes (5nm/3nm/2nm), and lead a team of high-performing engineers.

Key Responsibilities

• Strategy & P&L: Define the practice roadmap, drive revenue growth, manage utilization, and oversee business unit P&L.
• Client Engagement: Partner with sales to lead RFPs, technical proposals, and client technical governance for global semiconductor accounts.
• Delivery Excellence: Provide technical leadership across Synthesis, Floorplanning, CTS, Routing, STA, and PV (DRC/LVS/EMIR) for complex SoCs/ASICs.
• Team Leadership: Build, mentor, and scale a world-class engineering team in Bangalore.

Key Qualifications

• B.E./B.Tech/M.Tech in Microelectronics, VLSI, or Electronics Engineering.
• 15+ years in VLSI Physical Design with 5+ years leading practice/business units.
• Proven tape-out track record on sub-7nm FinFET/GAA nodes.
• Expertise in Synopsys (Fusion Compiler, PrimeTime) or Cadence (Innovus, Tempus) EDA suites.