Physical Design Director

Mulya Technologies; Hyderabad; On-site; INR 4,000,000 - 9,000,000; Full time

Job summary

Top40 Semiconductor Organization in the world seeks a senior Physical Design Lead in Hyderabad to head and grow the PD function. The role focuses on leading a high-performing team, driving full-chip implementation, and establishing best-in-class design flows for complex ASICs.

The ideal candidate will have deep hands-on PD expertise, a proven tapeout track record, and the leadership ability to scale a global team across PD, RTL, DV, DFT, and packaging groups.

Qualifications

• 18+ years in ASIC physical design with leadership experience.
• Hands-on with full-chip PD: floorplanning, PnR, CTS, STA, IR/EM, and PD verification.
• Proven tapeout track record at 7nm or below; 5nm/3nm preferred.
• Experience leading global PD teams and cross-functional partners.
• Strong scripting in Tcl or Python; CAD tool proficiency.

Responsibilities

• Lead and mentor the Hyderabad PD team across PnR, STA, and PD flows.
• Own end-to-end physical implementation of complex SoCs from floorplanning to GDSII.
• Drive floorplanning, CTS, routing, timing closure, IR/EM, and physical verification.
• Collaborate with RTL, DV, DFT, packaging, and architecture teams.
• Define team structure, hiring roadmap, and career paths.
• Oversee tapeout schedules and cross-functional dependencies.

Skills

Leadership

Physical design

Tapeouts

Scripting (Tcl/Python)

EDA tools

Education

Bachelor's/Master's in EE/CS

Tools

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime

Calibre

RedHawk

Voltus

Job description

Top40 Semiconductor Organization in the world

Role Overview

We are seeking a Physical Design Director to lead and grow our Physical Design function in Hyderabad. This is a senior leadership role responsible for building and managing a high-performing PD team, driving physical implementation of complex, high-speed connectivity ASICs, and establishing best-in-class design methodology and flows.

The ideal candidate brings deep hands-on expertise in full-chip physical design at advanced nodes, a proven track record of successful tapeouts, and the leadership ability to scale a team and deliver results in a fast-paced, high-growth environment. This role will work closely with global PD, RTL, DV, DFT, and packaging teams to ensure first-pass silicon success.

Key Responsibilities

• Build, lead, and mentor a high-performing Physical Design team in Hyderabad across PnR, STA, EMIR/Power Integrity, and CAD/methodology fun
• ctionsDefine team structure, hiring roadmap, and career development paths for PD eng
• ineersFoster a culture of technical excellence, ownership, and continuous impro
• vementPartner with global PD leadership (US and Israel sites) to align on strategy, methodology, and execution priorities
• Physical Design Execution
• Own end-to-end physical implementation of complex SoCs/ASICs from floor planning through GDSII
• signoffDrive floor planning, placement, clock tree synthesis (CTS), routing, timing closure, power analysis (IR drop/EM), and physical verification (D
• RC/LVS)Lead timing closure across multiple corners and modes (MMMC), ensuring robust STA signoff at advanced nodes (5nm and
• below)Oversee power integrity and reliability analysis (IR drop, EM) to meet design quality and manufacturability
• targetsManage tapeout schedules,milestones, and cross-functional dependencies to deliver on time and within PPAtargetsMethodology & CAD
• Establish and continuously improve PD flows, methodologies, checklists, and best practices for first-pass
• successEvaluate and deploy EDA tools (Cadence Innovus, Synopsys Fusion Compiler, PrimeTime, Calibre, RedHawk/Voltus, StarRC, etc.)Drive automation and scripting (Tcl, Python, Perl) to improve turnaround time and design
• qualityCollaborate with EDA vendors on tool evaluation, adoption, and methodology improvements
• Cross-Functional Collaboration
• Partner closely with RTL, DV, DFT, packaging, and architecture teams to enable seamless integration of complex subsystems (SerDes, high-speed PHYs, die-to-die interfaces, etc.)Provide physical design input during architecture and floorplan feasibility studies, die sizing, and IP evaluationRepresent the Hyderabad PD team in global design reviews, tapeout readiness reviews, and leadership forums
• Basic Qualifications
• Bachelor's or master’s degree in electrical engineering, Electronics, or Computer Science18+ years of experience in ASIC physical design, with at least 5 years in a leadership or management roleShould be hands on with a proven track record of multiple successful tapeouts at advanced nodes (7nm or below); experience at 5nm/3nm strongly
• preferred
• Deep hands-on expertise in full-chip physical design: floorplanning, PnR, CTS, STA, IR/EM analysis, and physical verification
• Strong proficiency with industry-standard EDA tools: Cadence Innovus, Synopsys Fusion Compiler/IC Compiler, PrimeTime, Calibre, RedHawk/Voltus
• Experience with high-speed interface IPs such as SerDes, PCIe, CXL, or die-to-die (D2D/UCIe) interconnects
• Strong scripting skills in Tcl, Python, or Perl
• Demonstrated ability to build and lead global, cross-functional engineering teams
• Preferred Qualifications
• Experience with chiplet architecture, UCIe interfaces, or die-to-die physicalintegration
• Familiarity with low-power design techniques (UPF/CPF, multi-voltage domains)
• Experience working with TSMC advanced nodes and TSMC tapeout processes
• Background in networking, storage, or AI/ML
• Strong cross-functional collaboration skills with RTL, DFT, packaging, and silicon opera
• tions teams
• Experience establishing a PD center of excellence or greenfeld PDteam