Physical Design Layout Engineer ICE

Intel; Bengaluru; Hybrid; INR 600,000 - 900,000; Full time

Job summary

Intel is seeking a Physical Design Engineer in Bengaluru to contribute to chip layouts at the physical level. You will work on cell and block-level semi-custom layouts, floor planning, and schematic-to-layout verification as part of a hybrid team.

The role targets candidates with 0–1 years of hands-on experience, including internships or coursework in electronics or electrical engineering. TCL scripting and ICC2 familiarity are appreciated assets.

Qualifications

• Bachelor's or Master's degree in Electronics/Electrical Engineering with 0–1 years hands-on physical design experience or internship.
• Basic understanding of layout design and verification processes.
• Familiarity with ICC2 tools.
• Proficiency or exposure to TCL scripting is a plus.

Responsibilities

• Develop and refine physical chip designs including cell- and block-level layouts and floor plans.
• Perform schematic-to-layout verification and ensure design integrity.
• Conduct reliability verification and debug design issues to optimize performance.
• Utilize physical design flows, parasitic extraction, and auto-place/route techniques to deliver robust layouts.
• Collaborate across teams to address complex design challenges.

Skills

ICC2 tools familiarity

TCL scripting

Layout design knowledge

Analytical problem-solving

Education

Bachelor's degree in Electronics/Electrical Engineering

Master's degree in Electronics/Electrical Engineering (no professional experience)

Tools

ICC2 tools

Job description

The Role and Impact

As a Physical Design Engineer, you will focus on creating and optimizing chip designs at the physical level. You'll be responsible for crafting elements such as cell, block-level semi‑custom layouts, FUB-level floor plans, and performing schematic-to-layout verification to ensure design integrity. Your contributions will directly impact the development and execution of complex chip methodologies, enabling Intel to deliver cutting‑edge technology to the marketplace.

Business group

This role is part of Intel's broader semiconductor engineering organization, which is dedicated to designing, developing, and verifying innovative chip technologies. The team focuses on advancing physical design methodologies, ensuring reliability, and optimizing chip performance while supporting Intel's mission to create world‑class computing solutions.

Key Responsibilities

• Develop and refine physical chip designs, including cell and block-level semi‑custom layouts, FUB-level floor plans, abstract view generation, and schematic‑to‑layout verification.
• Conduct reliability verification, debug issues, and apply proactive intervention strategies to optimize chip performance.
• Utilize parasitic extraction, custom polygon editing, auto‑place and route algorithms, floor planning, and full‑chip assembly techniques to ensure design success.
• Collaborate across teams to troubleshoot complex design challenges and deliver high‑quality solutions.
• Participate in the execution of project methodologies, flow developments, and verification processes.

Qualifications

Minimum Qualifications

• Bachelor's degree in Electronics, Electrical Engineering, or a related field with 0‑1 years of hands‑on experience in physical design, including skills gained through internships, academic projects, coursework, or hands‑on training OR a Master's degree in Electronics, Electrical Engineering, or a related field with no prior professional experience.
• Basic understanding of layout design and verification processes.
• Familiarity with ICC2 tools.
• Proficiency in TCL scripting is a plus.

Preferred Qualifications

• Strong problem‑solving skills and ability to troubleshoot complex design challenges effectively.
• Excellent collaboration and communication skills to work across diverse teams.
• Demonstrated interest in advancing semiconductor technologies and methodologies.

We’re excited to see how your skills and passion for innovation can contribute to our cutting‑edge team.

Job Type: Intel Contract Employee

Shift: Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust: N/A

Work Model for this Role: This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees…/