Physical Design Engineer

Intel Corporation; India; Hybrid; INR 1,500,000 - 2,100,000; Full time

Benefits offered by this job

Hybrid work model

Job summary

Intel Corporation seeks experienced Physical Design Engineers to translate RTL to GDS and deliver manufacturing-ready design databases for custom IP and SoC designs. You will drive the full physical design flow from synthesis to signoff, including STA, upload of clock and power integrity checks, and DFT considerations.

Role emphasizes optimization of power, performance, and area, plus collaboration across cross-functional teams to enhance methodologies and flow automation.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 5+ years of experience in Physical Design execution.
• Master's degree with 3+ years of experience in Physical Design execution.
• Deep knowledge in RTL-to-GDS workflows, including synthesis, place and route, and static timing analysis.
• Expertise in optimization techniques for power, performance, and area (PPA).
• Hands-on experience with industry-standard EDA tools for physical design and verification.
• Comprehensive knowledge of clock tree synthesis and low-power design techniques.
• Experience with competitive timing, floor planning methodologies (TFM), and multi-power domain analysis.

Responsibilities

• Translate RTL to GDS and create manufacturing-ready design databases.
• Perform physical design flows: synthesis, place-and-route, clock tree synthesis, floor planning, timing analysis, power integrity.
• Verify and signoff: formal equivalence, static timing, reliability, power integrity, layout checks, DRC/LVS.
• Analyze results and fix violations; optimize for power, performance, and area.
• Collaborate across teams to improve physical design methodologies and flow automation.

Skills

RTL-to-GDS workflows

Synthesis

Place and route

Static timing analysis

Power/clock distribution

DFT

EDA tools

Clock tree synthesis

Floor planning

Multi-power domain analysis

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree in Electrical/Computer Engineering

Tools

EDA tools

Job description

Job Details: Job Description: Intel Central Engineering Group is seeking Physical Design Engineers to join our dynamic team and contribute to the development of cutting-edge custom IP and SoC designs for Intel products and Intel Custom ASIC Customers.

In this role, you will play a pivotal part in translating RTL to GDS, enabling manufacturing-ready design databases that drive innovation in products.

Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Qualifications: Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 5+ Years of experience in Physical Design execution.
• Master's degree with 3+ Years of experience in Physical Design execution.
• Deep knowledge in RTL-to-GDS workflows, including synthesis, place and route, and static timing analysis.
• Expertise in optimization techniques for power, performance, and area (PPA).
• Hands-on experience with industry-standard EDA tools for physical design and verification.
• Comprehensive knowledge of clock tree synthesis and low-power design techniques.
• Experience with competitive timing, floor planning methodologies (TFM), and multi-power domain analysis.

Preferred Qualifications:

• Demonstrated ability to collaborate within cross-functional teams to achieve strategic design goals.
• Strong critical thinking and problem-solving skills to manage complex design challenges.
• Excellent communication and organizational abilities to coordinate across disciplines.
• A passion for innovation and continuous improvement in design methodologies.

Job Type: Experienced Hire

Shift: Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off‑site.

* Job posting details (such as work model, location or time type) are subject to change.

* ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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