Physical Design Engineer

Texas Instruments India; Bengaluru; On-site; INR 800,000 - 1,200,000; Full time

Job summary

Texas Instruments India is looking for a Physical Design Engineer to join its team in Bengaluru. This position requires expertise in physical design for complex mixed-signal devices, focusing on RTL design and EDA tool usage.

The ideal candidate will have 2–5 years of experience and a relevant degree, alongside strong skills in timing analysis, scripting, and problem-solving. Texas Instruments values diversity and offers a supportive workplace environment for all employees.

Qualifications

• 2–5 years of hands-on experience in physical design for ASIC/SoC.
• Strong knowledge of CMOS, VLSI design fundamentals, and digital circuit concepts.
• Experience in sign-off checks: DRC, LVS, IR-drop, EM, noise analysis.

Responsibilities

• Execute RTL-to-GDSII physical design flow for complex SoC/ASIC blocks.
• Perform logic synthesis, floor-planning, placement, clock tree synthesis (CTS), and routing.
• Drive timing closure across multiple corners and modes using static timing analysis (STA).
• Optimize for area, power, and performance (PPA) at block and chip level.

Skills

RTL design

Timing analysis

Scripting (TCL/Perl/Python)

Physical design tools (Cadence)

Problem-solving

Education

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI, or related field

Tools

Cadence (Innovus, Tempus, Voltus)

EDA tools

Job description

About The Role

We are looking for a Physical Design Engineer to join the team of enthusiastic engineers who develop highly complex mixed‑signal devices for audio applications with industry‑leading performance. This role requires a skilled Digital Physical Design Engineer with 2‑5 years of industry experience, good RTL design hands‑on ability, and understanding of digital VLSI concepts. The candidate will be responsible for taking RTL through synthesis, floorplanning, place‑and‑route, timing closure, power optimization, and physical verification to tape‑out, using EDA tools and physical design flows.

Key Responsibilities

• Execute RTL‑to‑GDSII physical design flow for complex SoC/ASIC blocks.
• Perform logic synthesis, floor‑planning, placement, clock tree synthesis (CTS), and routing.
• Develop, support, and update design constraints.
• Drive timing closure across multiple corners and modes using static timing analysis (STA).
• Apply good understanding of digital timing analysis.
• Optimize for area, power, and performance (PPA) at block and chip level.
• Conduct physical verification: DRC, LVS, antenna checks, IR‑drop, and EM analysis.
• Collaborate with RTL design, verification, and architecture teams to resolve design and implementation issues.
• Provide EDA flow automation support (scripting in TCL/Perl/Python).
• Contribute to design reviews, documentation, and sign‑off processes for successful tape‑out.
• Highly preferred: handle RTL coding, digital QC (RDC/CDC/Lint). Contribute to digital design reviews and architecture reviews.

Qualifications

• B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI, or related field.
• 2–5 years of hands‑on experience in physical design for ASIC/SoC.
• Strong knowledge of CMOS, VLSI design fundamentals, and digital circuit concepts.
• Proficiency in EDA tools such as Cadence (Innovus, Tempus, Voltus) or equivalent.
• Experience in sign‑off checks: DRC, LVS, IR‑drop, EM, noise analysis.
• Strong scripting skills (TCL, Perl, or Python) for flow automation.
• Excellent problem‑solving, debugging, and analytical skills.
• Expertise in timing analysis, floorplanning, placement, CTS, routing, and optimization techniques.
• Hands‑on experience with Cadence simulation tools.
• Knowledge of audio signal chain, I2C, ASI/TDM, memory architecture and FPGA is preferred.
• Excellent debugging and problem‑solving skills.

Additional Preference

• Digital design fundamentals and basic electrical/electronic engineering concepts.
• Hands‑on experience in RTL design coding with understanding of QC (Lint/CDC/RDC) is highly preferred and recommended.

Soft Skills

• Strong communication, presentation and collaboration skills.
• Ability to work in a fast‑paced, deadline‑driven environment.
• Self‑motivated and detail‑oriented with a commitment to quality.

Benefits and EEO Statement

Texas Instruments is an equal‑opportunity employer and supports a diverse, inclusive work environment.