Physical Design Engineer | ASIC Physical Design Engineer (PnR/STA)

Erbity; Dadri; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Erbity in India (UP) is seeking a Physical Design Engineer to own the silicon journey from floorplanning through signoff. The role emphasizes hands-on PnR/STA, EM/IR closure, and strong collaboration to meet aggressive PPA targets.

Experience with clock tree, routing optimization, and extraction is essential, along with exposure to automation and flow improvements to drive efficiency and quality in the ASIC design flow.

Qualifications

• 5-25 years in physical design and SoC implementation.
• Hands-on with floorplanning, PnR, STA, and EM/IR closure.
• Experience in clock tree, routing optimization, and extraction.
• Proven ability to meet aggressive PPA targets.
• Exposure to automation and flow improvements.
• Strong collaboration and execution mindset.

Responsibilities

• Own the silicon journey from floorplan to signoff.
• Lead PnR/STA optimization and verify timing closure.
• Collaborate across teams to meet PPA targets.

Skills

Floorplanning

PnR

STA

EM/IR closure

ASIC design flow

Signoff

Automation

Collaboration

Tools

Innovus

Tempus

Voltus

Quantus

Job description

Physical Design Engineer | ASIC Physical Design Engineer (PnR/STA)

This role is about owning the silicon journey from floorplan to signoff.

Requirements

• 5-25 years in physical design and SoC implementation
• Strong experience in Cadence tools: Innovus, Tempus, Voltus, Quantus
• Hands‑on with floorplanning, PnR, STA, and EM/IR closure
• Proven ability to meet aggressive PPA targets
• Experience in clock tree, routing optimization, and extraction
• Strong understanding of ASIC design flow and signoff
• Exposure to automation and flow improvements
• Strong collaboration and execution mindset

If PPA targets excite you more than scare you, this one's for you.