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Erbity is seeking a Physical Design Engineer for ASIC flow from floorplanning to signoff. You will own the silicon journey, driving PnR/STA, EM/IR closure, and signoff readiness with a strong focus on PPA targets.
The role requires hands-on experience with Cadence Innovus, Tempus, Voltus, and Quantus, plus a solid understanding of clock tree, routing optimization, and extraction. Collaboration and automation improvements are valued.
This role is about owning the silicon journey from floorplan to signoff.
If PPA targets excite you more than scare you, this one's for you.