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Erbity Private Limited is seeking a seasoned Physical Design Engineer to own the silicon journey from floorplanning to signoff. You will drive PnR/STA activities, optimize clock trees and routing, and ensure tight PPA targets are met with Cadence Innovus, Tempus, Voltus and Quantus.
Applicants should have 5–25 years in physical design, hands-on flow improvements, and strong collaboration to execute complex SoC implementations end-to-end.
This role is about owning the silicon journey from floorplan to signoff.
If PPA targets excite you more than scare you, this one’s for you.
Physical Design Engineer | ASIC Physical Design Engineer (PnR/STA)
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