Physical Design Engineer

Texas Instruments; Bengaluru; On-site; INR 800,000 - 1,200,000; Full time

Job summary

A leading technology firm in India is seeking a Physical Design Engineer to join its Connectivity team. This role involves optimizing designs for high-performance wireless connectivity solutions related to IoT and automotive applications. Responsibilities include floorplanning, placement and routing, clock tree synthesis, and power management. Ideal candidates should have a background in Electrical Engineering and familiarity with various EDA tools. This position provides opportunities to influence next-gen connectivity architectures and participate in mentorship programs.

Qualifications

• Experience with chip floorplanning, placement, and routing.
• Knowledge of clock tree synthesis and power grid strategies.
• Understand physical verification and resolution of DRC and LVS violations.

Responsibilities

• Create and optimize chip floorplans to meet various targets.
• Execute detailed routing for complex designs.
• Work with EDA vendors to improve design flows.

Skills

Floorplanning and optimization

Placement optimization

Clock Tree Synthesis

Power Planning

Physical Verification

Low power implementation

Signal Integrity analysis

Performance Optimization

Area Optimization

Cross-functional Collaboration

Education

Bachelor's degree in Electrical Engineering or related field

Tools

EDA tools

Job description

Physical Design Engineer - Texas Instruments

About the Role

Join Texas Instruments' Connectivity engineering team as a Physical Design Engineer, where you'll play a critical role in delivering high-performance wireless connectivity solutions that power next-generation IoT, automotive, and industrial applications.

What You'll Do

Physical Implementation

• Floorplanning: Create and optimize chip floorplans to meet performance, power, and area targets
• Placement & Routing: Execute placement optimization and detailed routing for complex SoC designs
• Clock Tree Synthesis (CTS): Design and implement robust clock distribution networks with minimal skew and jitter
• Power Planning: Develop comprehensive power grid strategies including power ring, stripes, and via insertion
• Flow and tool improvements: Work with EDA vendors, TI internal EDA teams to improve flow recipes, implement automations and improve design QoR

Design Verification & Analysis

• Physical Verification: Execute and resolve DRC (Design Rule Check) and LVS (Layout vs. Schematic) violations
• Power management: Execute and verify lower power checks to ensure power management integrity
• Low power implementation: Conduct dynamic and static power analysis to meet power budgets
• Signal Integrity: Address crosstalk, IR drop, and electromigration issues

Design Optimization

• Performance Optimization: Fine-tune design to meet frequency and timing requirements
• Area Optimization: Minimize die size while maintaining functionality and performance
• Yield Enhancement: Implement design-for-manufacturing (DFM) techniques

Collaboration & Documentation

• Cross-functional Collaboration: Work closely with front-end designers, verification teams, and package engineers
• Documentation: Create and maintain comprehensive design documentation and flow methodologies
• Mentorship: Provide guidance to junior engineers and interns

Growth Opportunities

• Work on both established connectivity platforms and breakthrough wireless technologies
• Contribute to multiple tape‑outs annually across different process nodes
• Influence next‑generation connectivity architecture decisions
• Mentorship opportunities with junior engineers and cross‑functional collaboration

Why This Role

• Direct impact on TI's wireless connectivity portfolio performance
• Exposure to diverse wireless standards and emerging technologies
• Opportunity to work with state‑of‑the‑art EDA tools and methodologies
• Be part of innovation initiatives including new wireless technologies for TI

Technical Environment

• Multiple process technology nodes and design rule sets
• Complex mixed-signal connectivity SoC designs
• Automated flow development and optimization